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| - 1 - K4P4G304EC rev. 0.5, sep. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. preliminary 4gb ddp lpddr2-s4 sdram 134fbga, 11x11.5, 2/cs, 2cke 64m x32 + 64m x32 datasheet http:///
- 2 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 revision history revision no. history draft date remark editor 0.0 - first version for target specification. sep. 13, 2010 target j.y.bae - k4p2g16(32)4c(e)c-ag_ver 1.0 0.1 - corrected errata. sep. 15, 2010 target j.y.bae - revised package ballout 1. deleted zq1 0.5 - preliminary datasheet. sep. 30, 2010 preliminary j.y.bae - corrected typo. - revised dc characteristics. http:/// - 3 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 table of contents 4gb ddp lpddr2-s4 sdram 1.0 key feature ........... ............... .............. .............. .............. ........... ........... ........... ........... ........................................... 5 2.0 ordering information ....................................................................................................... ............................... 5 3.0 lpddr2 sdram addressing ............ .............. .............. .............. .............. ........... ........... .......... ........................... 6 4.0 package dimension & pin description ........................................................................................ ................. 7 4.1 lpddr2 sdram package dimension . ............. .............. .............. .............. .............. .............. ......... ...................... 7 4.2 lpddr2 sdram package ballout ...... .............. .............. .............. .............. ........... ........... ........... .......................... 8 4.3 input/output functional description................ ........................................................................ ................................... 9 4.3.1 functional block diagram ............................ ..................................................................... ................................ 9 4.4 input/output functional description................ ........................................................................ ................................... 10 4.4.1 pin definition and descripti on ........................................................................................... ................................ 10 5.0 functional description ..................................................................................................... .............................. 11 5.1 simplified lpddr2-s4 state diagram ............... .............. .............. .............. ........... ........... .......... ........................... 12 5.2 mode register definition ................................................................................................... ...................................... 13 5.2.1 mode register assignment and definition in lpddr2 sdram ......... .............. ........... ........... ........... .......... ..... 13 6.0 truth tables ............................................................................................................... .......................................... 22 6.1 truth tables ............................................................................................................... ............................................. 22 6.1.1 command truth table...................................................................................................... ................................... 23 6.2 lpddr2-sdram truth tables ......... .............. .............. .............. .............. ........... ........... ........... ............................. 25 6.3 data mask truth table ...................................................................................................... ........................................ 28 7.0 absolute maximum dc ratings .... .............. .............. .............. .............. .............. ........... ........... ....................... 29 8.0 ac & dc operating conditions............................................................................................... ......................... 30 8.1 recommended dc operating conditions ..................... ................................................................... ....................... 30 8.2 input leakage current ...................................................................................................... ....................................... 30 8.3 operating temperature range................................................................................................ ................................ 30 9.0 ac and dc input measurement l evels ............ .............. .............. .............. .............. ........... .......... ................ 31 9.1 ac and dc logic input levels for single-ended sig nals ............... .............. .............. .............. ............. .................. 31 9.1.1 ac and dc input levels for single-ended ca and cs signals ....... .............. ........... ........... ............ ......... ........ 31 9.2 ac and dc input levels for cke ............................................................................................. ............................... 31 9.2.1 ac and dc input levels for single-ended data si gnals ........... .............. ............ ........... ........... .......... ............. 31 9.3 vref tolerances ............................................................................................................ ........................................... 32 9.4 input signal.............. ............... .............. .............. .............. .............. .............. ............ ............................................... 33 9.5 ac and dc logic input levels for differential signa ls ...................................................................... ...................... 34 9.5.1 differential signal definition ........................................................................................... .................................... 34 9.5.2 differential swing requirements for clock (ck - ck) and strobe (dqs - dqs)............................................... ... 34 9.5.3 single-ended requirements for differential signals . ...................................................................... ..................... 36 9.6 differential input cross point voltage................. .................................................................... ................................. 37 9.7 slew rate definitions for single-ended input signal s .............. .............. ........... ........... ............ ......... ...................... 38 9.8 slew rate definitions for differential input signa ls ....................................................................... .......................... 38 10.0 ac and dc output measurement levels ............ .............. .............. .............. ........... ........... ........... ............ 39 10.1 single ended ac and dc output levels...................................................................................... ......................... 39 10.2 differential ac and dc output levels ................ ...................................................................... ............................. 39 10.3 single ended output slew rate ....................... ...................................................................... ............................... 40 10.4 differential output slew rate ............................................................................................. ................................... 41 10.5 overshoot and undershoot specifications ............... .............. .............. .............. .............. ............ ......................... 42 11.0 output buffer characteristics ............................................................................................. .................... 43 11.1 hsul_12 driver output timing reference load ............................................................................... ................... 43 12.0 ronpu and ronpd resistor definition....................................................................................... ............... 44 12.1 ronpu and ronpd characteristics with zq calibration ....................................................................... ............. 45 12.2 output driver temperature and voltage sensitivity ......................................................................... ..................... 45 12.3 ronpu and ronpd characteristics without zq calibration ...... .............. .............. .............. ........... ......... ........... 46 12.4 rzq i-v curve............................................................................................................. .......................................... 47 13.0 input/output capacitance .................................................................................................. ........................... 49 14.0 idd specification parameters and test conditions .......................................................................... .50 14.1 idd measurement conditions ................................................................................................ ............................... 50 14.2 idd specifications ........................................................................................................ ......................................... 51 http:/// - 4 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 14.3 idd spec table ............................................................................................................ ......................................... 54 15.0 electrical characteristics and ac timing........ .......................................................................... ........... 56 15.1 clock specification ....................................................................................................... ......................................... 56 15.1.1 definition for tck(avg) and nck.............. .............. .............. .............. ........... ........... ........... ............................. 56 15.1.2 definition for tc k(abs)................................................................................................. .................................... 56 15.1.3 definition for tch(avg) and tcl(avg).................................................................................... ........................... 56 15.1.4 definition for tjit(per) . ............................................................................................... ..................................... 56 15.1.5 definition for tj it(cc) ................................................................................................. ...................................... 57 15.1.6 definition for terr(nper) .. ............................................................................................. .................................. 57 15.1.7 definition for duty cycle jitter tjit(duty) ............................................................................. .............................. 57 15.1.8 definition for tck(abs), tch(abs) and tcl(abs). ......................................................................... ..................... 57 15.2 period clock jitter ....................................................................................................... .......................................... 58 15.2.1 clock period jitter effects on co re timing parameters . .................................................................. ................... 58 15.2.1.1 cycle time de-rating for core timing paramet ers...................................................................... ................ 58 15.2.1.2 clock cycle de-rating for core timing para meters..................................................................... ............... 58 15.2.2 clock jitter effects on command/address timing pa rameters ............................................................... .......... 58 15.2.3 clock jitter effects on read timing parameters .. .............. .............. ........... ........... ............ .......... ..................... 59 15.2.3.1 trpre................................................................................................................ ...................................... 59 15.2.3.2 tlz(dq), thz(dq), tdqsck, tlz(dqs), thz(dqs) ......................................................................... ........ 59 15.2.3.3 tqsh, tqsl........................................................................................................... ................................... 59 15.2.3.4 trpst ................................................................................................................ ...................................... 59 15.2.4 clock jitter effects on write timing parameters ......................................................................... ....................... 59 15.2.4.1 tds, tdh............................................................................................................. ...................................... 59 15.2.4.2 tdss, tdsh........................................................................................................... ................................... 59 15.2.4.3 tdqss................................................................................................................ ...................................... 60 15.3 lpddr2-s4 refresh requirement per device density .......................................................................... .............. 60 15.4 ac timings ................................................................................................................ ............................................ 61 15.5 ca and cs setup, hold and dera ting .............. .............. .............. .............. ........... ........... .......... ........................... 65 15.6 data setup, hold and slew rate derating ................................................................................... ......................... 71 http:/// - 5 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 lpddr2-s4 sdram specification 4g = 64m x 32 + 64m x 32 (8m x 32 x 8 banks + 8m x 32 x 8 banks) 2/cs, 2cke 1.0 key feature ? double-data rate architecture; two data transfers per clock cycle ? bidirectional data strobes (dqs, dqs ), these are transmitted/received with data to be used in capturing data at the receiver ? differential clock inputs (ck and ck ) ? differential data strobes (dqs and dqs ) ? commands & addresses entered on both positive and negative ck edges; data and data mask referenced to both edges of dqs ? 8 internal banks for concurrent operation ? data mask (dm) for write data ? burst length: 4 (default), 8 or 16 ? burst type: sequential or interleave ? read & write latency : refer to table 47 lpddr2 ac timing table ? auto precharge option for each burst access ? configurable drive strength ? auto refresh and self refresh modes ? partial array self refresh and temperature compensated self refresh ? deep power down mode ? hsul_12 compatible inputs ? vdd1/vdd2/vddq/vddca : 1.8v/1.2v/1.2v/1.2v ? no dll : ck to dqs is not synchronized ? edge aligned data output, center aligned data input ? auto refresh duty cycle : 3.9us ? 2/cs, 2cke 2.0 ordering information K4P4G304EC-fgc1 note : 1) k4p4g304 e c-% : vdd1=1.8v, vdd2=1.2v, vddq=1.2v, vddca=1.2v part no. org. package temperature max frequency interface x32 11x11.5 134fbga (lead free, halogen free) tc=-25~85?c 800mbps (tck=2.50ns) hsul_12 http:/// - 6 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 3.0 lpddr2 sdram addressing [table 1] lpddr2 sdram addressing note : 1) the least-significant column address c0 is not transmitted on the ca bus, and is implied to be zero. 2) t refi values for all bank refresh is tc = -25~85 c, tc means operating case temperature 3) row and column address values on the ca bus that are not used are ?don?t care.? items 2gb device type s4 number of banks 8 bank addresses ba0-ba2 t refi (us) *2 3.9 x16 row addresses r0-r13 column addresses *1 c0-c9 x32 row addresses r0-r13 column addresses *1 c0-c8 http:/// - 7 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 4.0 package dimension & pin description 4.1 lpddr2 sdram package dimension 134-ball fine pitch ball grid array package (measured in millimeters) units:millimeters b 134- ? 0.300 0.05 0.20 m a b ? a #a1 1 3 5 2 4 6 7 89 10 bottom view top view 11.50 0.10 #a1 index u t r p n m l k j h g f e d c b a 0.22 0.05 0.80 0.10 0.08 max 11.00 0.10 11.50 0.10 side view (datum b) (datum a) 11.00 0.10 0.65 x 9 = 5.85 5.20 0.65 0.65 x 16 = 10.40 0.325 2.925 0.65 http:/// - 8 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 4.2 lpddr2 sdram package ballout [top view] 134ball fbga 1 2 3 4 5 6 7 8 9 10 a dnu dnu nb nb nb nb nb nb dnu dnu b dnu nc nc nb vdd2 vdd1 dq31 dq29 dq26 dnu c vdd1 vss nc nb vss vssq vddq dq25 vssq vddq d vss vdd2 zq nb vddq dq30 dq27 dqs3 dqs 3 vssq e vssca ca9 ca8 nb dq28 dq24 dm3 dq15 vddq vssq f vddca ca6 ca7 nb vssq dq11 dq13 dq14 dq12 vddq g vdd2 ca5 vref(ca) nb dqs 1 dqs1 dq10 dq9 dq8 vssq h vddca vss ck nb dm1 vddq nb nb nb nb j vssca nc ck nb vssq vddq vdd2 vss vref(dq) nb k cke0 cke1 nc nb dm0 vddq nb nb nb nb l cs 0cs 1ncnbdqs 0 dqs0 dq5 dq6 dq7 vssq m ca4 ca3 ca2 nb vssq dq4 dq2 dq1 dq3 vddq n vssca vddca ca1 nb dq19 dq23 dm2 dq0 vddq vssq p vss vdd2 ca0 nb vddq dq17 dq20 dqs2 dqs 2 vssq r vdd1 vss nc nb vss vssq vddq dq22 vssq vddq t dnu nc nc nb vdd2 vdd1 dq16 dq18 dq21 dnu u dnu dnu nb nb nb nb nb nb dnu dnu http:/// - 9 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 4.3 input/output functional description 4.3.1 fun 64mx32 64mx32 dq0~dq31 zq ck, ck , ca0~9, dm0~3, dqs0~3 dqs 0~3 cs 0, cke0 cs 1, cke1 vdd1/vdd2/ vddca/vddq/ vref/vss/ vssca/vssq ctional block diagram http:/// - 10 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 4.4 input/output functional description 4.4.1 pin definition and description [table 2] pin definition and description note : 1) data includes dq and dm. name type description ck, ck input clock: ck and ck are differential clock inputs. all double data ra te (ddr) ca inputs are sampled on both positive and negative edge of ck. single data rate (sdr) inputs, cs and cke, are sampled at the positive clock edge. clock is defined as the differential pair, ck and ck . the positive clock edge is defined by the crosspoint of a rising ck and a falling ck . the negative clock edge is defined by the cr osspoint of a falling ck and a rising ck . cke0, cke1 input clock enable: cke high activates and cke low deactivates internal clock signals and therefore device input buffers and output drivers. power savings modes ar e entered and exited through cke transitions. cke is considered part of the command code. see command truth table on page 23 for command code descriptions. cke is sampled at the positive clock edge. cs 0, cs 1 input chip select: cs is considered part of the command code. see command truth table on page 23 for command code descriptions. cs is sampled at the positive clock edge. ca0 - ca9 input ddr command/address inputs: uni-directional command/address bus inputs. ca is considered part of the command code. see comm and truth table on page 23 for command code descriptions. dq0 - dq31 i/o data inputs/outputs: bi-directional data bus dqs0 - dqs3 dqs 0 - dqs 3 i/o data strobes (bi-directional, differential): the data strobe is bi-directional (used for read and write data) and differential (dqs and dqs ). it is output with read data and input with write dat a. dqs is edge-aligned to read data and centered with write data. for x16, dqs0 and dqs 0 correspond to the data on dq0 - dq7, dqs1 and dqs 1 to the data on dq8 - dq15. for x32, dqs0 and dqs 0 correspond to the data on dq0 - dq7, dqs1 and dqs 1 to the data on dq8 - dq15, dqs2 and dqs 2 to the data on dq16 - dq23, dqs3 and dqs 3 to the data on dq24 - dq31. dm0 - dm3 input input data mask: dm is the input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm is for input only, the dm loading shall match the dq and dqs (or dqs ). for x32 devices, dm0 is the input data mask signal for the data on dq0-7, dm1 is the input data mask signal for the data on dq8-15, dm2 is the input data mask signal for the data on dq16-23 and dm3 is the input data mask signal for the data on dq24-31. v dd1 supply core power supply 1: core power supply. v dd2 supply core power supply 2: core power supply. v ddca supply input receiver power supply: power supply for ca0-9, cke, cs, ck, and ck input buffers. v ddq supply i/o power supply: power supply for data input/output buffers. v ref (ca) supply reference voltage for ca input receiver: reference voltage for all ca0-9, cke, cs, ck, and ck input buffers. v ref (dq) supply reference voltage for dq input receiver: reference voltage for all data input buffers. v ss supply ground v ssca supply ground for input buffers (receivers) v ssq supply i/o ground zq i/o reference pin for output drive strength calibration http:/// - 11 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 5.0 functional description this device contains the following number of bits: 4gb has 2,147,483,648 bits + 2,147,483,648 bits lpddr2-s4 uses a double data rate archiecture on the command/addr ess (ca) bus to reduce the number of input pins in the system. the 10-bit ca bus contains command, address, and bank information. each command uses one clock cycle, during whic h command information is transfe rred on both the positive and negative edge of the clock. lpddr2-s4 uses a double data rate architecture on the dq pins to achieve high speed operation. the double data rate architectur e is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per dq every clock cycl e at the i/o pins. a single r ead or write access for the lpddr2-s4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal sdram core and four corre sponding n-bit wide, one- half-clock-cycle data trans fers at the i/o pins. read and write accesses to the lpddr2 are burst oriented; accesses start at a selected location and continue for a programmed n umber of locations in a programmed sequence. for lpddr2-s4 devices, accesses begin with the registration of an activate comm and, which is then followed by a read or write c ommand. the address and ba bits registered coincident with the activate command are us ed to select the row and the bank to be accessed. the address bits registered coincident with the read or write command are used to select t he bank and the starting column location for the burst access. prior to normal operation, the lpddr2 must be initialized. http:/// figure 1. lpddr2-s4: simplified bus interface state diagram - 12 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 5.1 simplified lpddr2-s4 state diagram lpddr2-sdram state diagram provides a simplified illustration of allowed state transit ions and the related commands to control them. for a complete definition of the device behavior, the information provided by t he state diagram should be integrated with the truth tables and timing specification. the truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restr ictions when considering the actual state of all the banks. for the command definition, see datasheet of [command definition & timing diagram]. note : 1) for lpddr2-sdram in the idle state, all banks are precharged. self idle reading precharging writing act rd sref ref pd mrr pdx pdx pd wr automatic sequence command sequence rda wra refreshing refreshing power down active *1 with reading with active reading writing pr(a) = precharge (all) mrw = mode register write sref = enter self refresh ref = refresh pd = enter power down pdx = exit power down act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) srefx rd bst mr autoprecharge autoprecharge deep power dpdx power down on bst wr bst = burst terminate mrr = mode register read srefx = exit self refresh dpd = enter deep power down dpdx = exit deep power down mrr mrw dpd power applied mr writing mr reading resetting mr reading reset reset = reset is achieved through mrw command mrr rda wra reset resetting active down power idle idle pr, pra power down resetting pd pdx pr, pra http:/// - 13 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 5.2 mode register definition 5.2.1 mode register assignment and definition in lpddr2 sdram table 3 shows the 16 common mode registers for lpddr2 sdram and nv m. table 4 shows only lpddr2 sdram mode registers and table 5 shows only lpddr2 nvm mode registers. additionally table 6 shows rf u mode registers and reset command. each register is denoted as ?r? if it can be read but not writt en, ?w? if it can be written but not read, and ?r/w? if it can b e read and written. mode register read command shall be used to read a register. mode register write command shall be used to write a register. [table 3] mode register assignment in lpddr2 sdram(common part) [table 4] mode register assignment in lpddr2 sdram (sdram part) mr# ma <7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 0 00 h device info. r (rfu) rzqi (rfu) di dai 1 01 h device feature 1 w nwr (for ap) wc bt bl 2 02 h device feature 2 w (rfu) rl & wl 3 03 h i/o config-1 w (rfu) ds 4 04 h refresh rate r tuf (rfu) refresh rate 5 05 h basic config-1 r lpddr2 manufacturer id 6 06 h basic config-2 r revision id1 7 07 h basic config-3 r revision id2 8 08 h basic config-4 r i/o width density type 9 09 h test mode w vendor-specific test mode 10 0a h io calibration w calibration code 11:15 0b h ~0f h (reserved) (rfu) mr# ma <7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 16 10 h pasr_bank w bank mask 17 11 h pasr_seg w segment mask 18-19 12 h -13 h (reserved) (rfu) http:/// - 14 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 5] mode register assignment in lpddr2 sdram (nvm part) [table 6] mode register assignment in lpddr2 sdram (dq calibration and reset command) the following notes apply to table 3 mode r egister assignment in lpddr2 sdram(common part), table 4 mode register assignment i n lpddr2 sdram (sdram part), table 5 mode register assignment in lpddr2 sdram (nvm part), and table 6 mode register assignment in lpdd r2 sdram (dq calibration and reset command): note : 1) rfu bits shall be set to ?0? during mode register writes. 2) rfu bits shall be read as ?0? during mode register reads. 3) all mode registers that are specified as rfu or wr ite-only shall return undefined data when read and dqs, dqs shall be toggled. 4) all mode registers that are specified as rfu shall not be written. 5) writes to read-only registers shall have no impact on the functionality of the device. mr# ma <7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 20:31 14 h ~1f h (do not use) mr# ma <7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 32 20 h dq calibration pattern a r see "dq calibration" on operations & timiing diagram. 33:39 21 h ~27 h (do not use) 40 28 h dq calibration pattern b r see "dq calibration" on operations & timiing diagram. 41:47 29 h ~2f h (do not use) 48:62 30 h ~3e h (reserved) (rfu) 63 3f h reset w x 64:126 40 h ~7e h (reserved) (rfu) 127 7f h (do not use) 128:190 80 h ~be h (reserved for vendor use) (rfu) 191 bf h (do not use) 192:254 c0 h ~fe h (reserved for vendor use) (rfu) 255 ff h (do not use) http:/// - 15 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr0_device information (ma<7:0> = 00 h ) : note : 1) rzqi will be set upon completion of the mrw zq initialization calibration command. 2) if zq is connected to vddca to set default calibration, op[4:3] shall be set to 01. if zq is not conn ected to vddca, either op[4:3] = 01 or op[4:3] =10 might indicate a zq- pin assembly error. it is recommended that the assembly error is corrected. 3) in the case of possible assembly error (either op[4:3]=01 per note 4), the lpddr2 device will default to factory trim settin gs for ron, and will ignore zq calibration com- mands. in either case, the system may not function as intended. 4) in the case of the zq self-test returning a value of 11b, this result indicates that the device has detected a resistor conn ection to the zq pin. however, this result cannot be used to validate the zq resistor value or that the zq resistor tolerance meets the specified limits (i.e 240-ohm +/- 1%). mr1_device feature 1 (ma<7:0> = 01 h ) : note : 1) bl 16, interleaved is not an official combination to be supported. 2) programmed value in nwr register is the number of clock cycles which determines when to start internal precharge operation f or a write burst with ap enabled. it is deter- mined by ru(twr/tck). op7 op6 op5 op4 op3 op2 op1 op0 (rfu) rzqi (rfu) di dai dai (device auto-initializ ation status) read-only op<0> 0 b : dai complete 1 b : dai still in progress di (device information) read-only op<1> 0 b : s2 or s4 sdram 1 b : do not use rzqi (built in self test for rzq information) 1) read-only op4:op3 00 b : rzq self test not supported 01 b : zq-pin may connect to vddca or float 10 b : zq-pin may short to gnd 11 b : zq-pin self test completed, no error condition detected (zq-pin may not con- nect to vddca or float nor short to gnd) op7 op6 op5 op4 op3 op2 op1 op0 nwr (for ap) wc bt bl bl write-only op<2:0> 010 b : bl4 (default) 011 b : bl8 100 b : bl16 all others: reserved bt 1) write-only op<3> 0 b : sequential (default) 1 b : interleaved wc write-only op<4> 0 b : wrap (default) 1 b : no wrap (allowed for sdram bl4 only) nwr 2) write-only op<7:5> 001 b : nwr=3 (default) 010 b : nwr=4 011 b : nwr=5 100 b : nwr=6 101 b : nwr=7 110 b : nwr=8 all others: reserved http:/// - 16 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 7] burst sequence by bl, bt, and wc note : 1) c0 input is not present on ca bus. it is implied zero. 2) for bl=4, the burst address represents c1 - c0. 3) for bl=8, the burst address represents c2 - c0. 4) for bl=16, the burst address represents c3 - c0. 5) for no-wrap (nw), bl4, the burst shall not cross the page boundary and shall not cross sub-page boundary. the variable y may start at any address with c0 equal to 0 and may not start at any address in tab l e 8 below for the respective density and bus width combinations. [table 8] lpddr2-s4 non wrap restrictions note : 1) non-wrap bl=4 data-orders shown above are prohibited. c3 c2 c1 c0 wc bt bl burst cycle number and burst address sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 0 b 0 b wrap any 4 0123 x x 1 b 0 b 2301 x xx 0 b nw any y y+1 y+2 y+3 x 0 b 0 b 0 b wrap seq 8 01234567 x 0 b 1 b 0 b 23456701 x 1 b 0 b 0 b 45670123 x 1 b 1 b 0 b 67012345 x 0 b 0 b 0 b int 01234567 x 0 b 1 b 0 b 23016745 x 1 b 0 b 0 b 45670123 x 1 b 1 b 0 b 67452301 xxx 0 b nw any illegal (not allowed) 0 b 0 b 0 b 0 b wrap seq 16 0123456789abcdef 0 b 0 b 1 b 0 b 23456789abcdef01 0 b 1 b 0 b 0 b 456789abcdef0123 0 b 1 b 1 b 0 b 6789abcdef012345 1 b 0 b 0 b 0 b 89abcdef01234567 1 b 0 b 1 b 0 b abcdef0123456789 1 b 1 b 0 b 0 b cdef0123456789ab 1 b 1 b 1 b 0 b ef0123456789abcd xxx 0 b int illegal (not allowed) xxx 0 b nw any illegal (not allowed) 2gb not across full page boundary x16 3fe, 3ff, 000, 001 x32 1fe, 1ff, 000, 001 not across sub page boundary x16 1fe, 1ff, 200, 201 x32 none http:/// - 17 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr2_device feature 2 (ma<7:0> = 02 h ): mr3_i/o configuration 1 (ma<7:0> = 03 h ): op7 op6 op5 op4 op3 op2 op1 op0 (rfu) rl & wl rl & wl write-only op<3:0> 0001 b : rl3 / wl1(default) 0010 b : rl4 / wl2 0011 b : rl5 / wl2 0100 b : rl6 / wl3 0101 b : rl7 / wl4 0110 b : rl8 / wl4 all others: reserved op7 op6 op5 op4 op3 op2 op1 op0 (rfu) ds ds write-only op<3:0> 0000 b : reserved 0001 b : 34.3-ohm typical 0010 b : 40-ohm typical (default) 0011 b : 48-ohm typical 0100 b : 60-ohm typical 0101 b : reserved for 68.6-ohm typical 0110 b : 80-ohm typical 0111 b : 120-ohm typical all others: reserved http:/// - 18 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr4_device temperature (ma<7:0> = 04 h ) note : 1) a mode register read from mr4 will reset op7 to ?0?. 2) op7 is reset to ?0? at power-up. op[2:0] bits are undefined after power-up. 3) if op2 equals ?1?, the device temperature is greater than 85?c. 4) op7 is set to ?1? if op2:op0 has changed at any time since the last read of mr4. 5) lpddr2 might not operate properly when op[2:0] = 000 b or 111 b 6) for specified operating temperature range and maximum operating temperature refer to table 17 operating temperature range . 7) lpddr2-s4 devices shall be de-rated by adding 1.875 ns to th e following core timing parameters : trcd, trc, tras, trp, and tr rd. tdqsck shall be de-rated according to the tdqsck de-rating in table 47 lpddr2 ac timing table . prevailing clock frequency s pec and related setup and hold timings shall remain unchanged. 8) see "temperature sensor" on [command definition & timing diagram] for information on the recommended frequency of reading mr 4. mr5_basic configurat ion 1 (ma<7:0> = 05 h ): op7 op6 op5 op4 op3 op2 op1 op0 tuf (rfu) sdram refresh rate sdram refresh rate read-only op<2:0> 000 b : sdram low temperature operating limit exceeded 001 b : 4x t refi, 4x t refipb, 4x t refw 010 b : 2x t refi, 2x t refipb, 2x t refw 011 b : 1x t refi, 1x t refipb, 1x t refw (<=85'c) 100 b : reserved 101 b : 0.25x t refi , 0.25x t refipb, 0.25x t refw, do not de-rate sdram ac timing 110 b : 0.25x t refi , 0.25x t refipb, 0.25x t refw, de-rate sdram ac timing 111 b : sdram high temperature operating limit exceeded temperature update flag (tuf) read-only op<7> 0 b : op<2:0> value has not changed since last read of mr4. 1 b : op<2:0> value has changed since last read of mr4. op7 op6 op5 op4 op3 op2 op1 op0 lpddr2 manufacturer id lpddr2 manufacturer id read-only op<7:0> 0000 0000 b : reserved 0000 0001 b : samsung 0000 0010 b : do not use 0000 0011 b : do not use 0000 0100 b : do not use 0000 0101 b : do not use 0000 0110 b : do not use 0000 0111 b : do not use 0000 1000 b : do not use 0000 1001 b : do not use 0000 1010 b : reserved 0000 1011 b : do not use 0000 1100 b : do not use 0000 1101 b : do not use 0000 1110 b : do not use 0000 1111 b : do not use 1111 1110 b : do not use all others: reserved http:/// - 19 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr6_basic configurat ion 2 (ma<7:0> = 06 h ): note : 1) mr6 is vendor specific. mr7_basic configurat ion 3 (ma<7:0> = 07 h ): note : 1) mr7 is vendor specific. mr8_basic configurat ion 4 (ma<7:0> = 08 h ) : mr9_test mode (ma<7:0> = 09 h ): op7 op6 op5 op4 op3 op2 op1 op0 revision id1 revision id1 read-only op<7:0> 00000000 b : a-version op7 op6 op5 op4 op3 op2 op1 op0 revision id2 revision id2 read-only op<7:0> 00000000 b : a-version op7 op6 op5 op4 op3 op2 op1 op0 i/o width density type type read-only op<1:0> 00 b : s4 sdram 01 b : s2 sdram 10 b : do not use 11 b : reserved density read-only op<5:2> 0000 b : 64mb 0001 b : 128mb 0010 b : 256mb 0011 b : 512mb 0100 b : 1gb 0101 b : 2gb 0110 b : 4gb 0111 b : 8gb 1000 b : 16gb 1001 b : 32gb all others: reserved i/o width read-only op<7:6> 00 b : x32 01 b : x16 10 b : x8 11 b : do not use op7 op6 op5 op4 op3 op2 op1 op0 vendor-specific test mode http:/// - 20 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr10_calibration (ma<7:0> = 0a h ): note : 1) host processor shall not wr ite mr10 with ?reserved? values. 2) lpddr2 devices shall ignore calibration command when a ?reserved? value is written into mr10. 3) see ac timing table for the calibration latency. 4) if zq is connected to v ssca through r zq , either the zq calibration function (see "mode register write zq calibration command" on [command definition & timing dia- gram]) or default calibration (through the zqreset command) is supported. if zq is connected to v ddca , the device operates with default calibration, and zq calibration com- mands are ignored. in both cases, the zq connection shall not change after power is applied to the device. 5) lpddr2 devices that do not support calibration shall ignore the zq calibration command. 6) the mrw zq initialization calibration command will update mr0 to indicate rzq pin connection. mr_11:15_(reserved) (ma<7:0> = 0b h -0f h ): mr_16_pasr_bank mask (ma<7:0> = 010 h ): s4 sdram: note : 1) for 4 bank s4 sdram, only op<3:0> are used. op7 op6 op5 op4 op3 op2 op1 op0 calibration code calibration code write-only op<7:0> 0xff: calibration command after initialization 0xab: long calibration 0x56: short calibration 0xc3: zq reset others: reserved op7 op6 op5 op4 op3 op2 op1 op0 bank mask (4-bank or 8-bank) bank <7:0> mask 1) write-only op<7:0> 0 b : refresh enable to the bank (=unmasked, default) 1 b : refresh blocked (=masked) op bank mask 4 bank 8 bank 0 xxxxxxx1 bank 0 bank 0 1 xxxxxx1x bank 1 bank 1 2 xxxxx1xx bank 2 bank 2 3 xxxx1xxx bank 3 bank 3 4 xxx1xxxx - bank 4 5 xx1xxxxx - bank 5 6 x1xxxxxx - bank 6 7 1xxxxxxx - bank 7 http:/// - 21 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 mr17_pasr_segment mask (ma<7:0> = 011 h ): note : 1) this table indicates the range of row addresses in each masked segment. x is do not care for a particular segment. mr18-19_(reserved) (ma<7:0> = 012 h - 013 h ): mr20-31_(do not use) (ma<7:0> = 14 h -1f h ): mr32_dq calibration pattern a (ma<7:0>=20 h ): reads to mr32 return dq calibration pattern "a". s ee "dq calibration" on oper ations & timiing diagram. mr33:39_(do not use) (ma<7:0> = 21 h -27 h ): mr40_dq calibration pattern b (ma<7:0>=28 h ): reads to mr40 return dq calibration pattern "b". s ee "dq calibration" on oper ations & timiing diagram. mr41:47_(do not use) (ma<7:0> = 29 h -2f h ): mr48:62_(reserved) (ma<7:0> = 30 h -3e h ): mr63_reset (ma<7:0> = 3f h ): mrw only note : 1) for additional information on mrw reset see "mode register write command" on [command definition & timing diagram] . mr64:126_(reserved) (ma<7:0> = 40 h -7e h ): mr127_(do not use) (ma<7:0> = 7f h ): mr128:190_(reserved for vendor use) (ma<7:0> = 80 h -be h ): mr191_(do not use) (ma<7:0> = bf h ): mr192:254_(reserved for vendor use) (ma<7:0> = c0 h -fe h ): mr255:(do not use) (ma<7:0> = ff h ): op7 op6 op5 op4 op3 op2 op1 op0 segment mask segment <7:0> mask write-only op<7:0> 0 b : refresh enable to the s egment (=unmasked, default) 1 b : refresh blocked (=masked) 1gb 2gb/4gb 8gb segment op segment mask r12:10 r13:11 r14:12 0 0 xxxxxxx1 000 b 1 1 xxxxxx1x 001 b 2 2 xxxxx1xx 010 b 3 3 xxxx1xxx 011 b 4 4 xxx1xxxx 100 b 5 5 xx1xxxxx 101 b 6 6 x1xxxxxx 110 b 7 7 1xxxxxxx 111 b op7 op6 op5 op4 op3 op2 op1 op0 x http:/// - 22 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 6.0 truth tables 6.1 truth tables operation or timing that is not specifie d is illegal, and after such an event, in order to guarantee proper operation, the lpdd r2 device must be powered down and then restarted through the specified initia lization sequence before normal operation can continue. http:/// - 23 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 6.1.1 command truth table [table 9] command truth table sdr command pins ddr ca pins (10) sdram command cke cs ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 ck edge ck(n-1) ck(n) mrw hh l l l l l ma0 ma1 ma2 ma3 ma4 ma5 x ma6 ma7 op0 op1 op2 op3 op4 op5 op6 op7 mrr hh l l l l h ma0 ma1 ma2 ma3 ma4 ma5 x ma6 ma7 x refresh (per bank) 10 hh l l l h l x x x refresh (all bank) hh l l l h h x x x enter self refresh h l l l l h x x x x activate (bank) hh l l h r8/a15 r9/a16 r10/a17 r11/a18 r12/a19 ba0 ba1 ba2 x r0/a5 r1/a6 r2/a7 r3/a8 r4/a9 r5/a10 r6/a11 r7/a12 r13/a13 r14/a14 write (bank) hh l h l l rfu rfu c1 c2 ba0 ba1 ba2 x ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 read (bank) hh l h l h rfu rfu c1 c2 ba0 ba1 ba2 x ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 precharge (pre bank, all bank) hh l h h l h ab/a30 x/a31 x/a32 ba0 ba1 ba2 x x/a20 x/a21 x/a22 x/a23 x/a24 x/a25 x/a26 x/a27 x/a28 x/a29 bst hh l h h l l x x x enter deep power down h l l h h l x x x x nop hh l h h h x x x maintain pd, sref, dpd (nop) ll l h h h x x x nop hh h x x x maintain pd, sref, dpd (nop) ll h x x x enter power down h l h x x x x exit pd, sref, dpd l h h x x x x http:/// - 24 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 note: 1) all lpddr2 commands are defined by states of cs , ca0, ca1, ca2, ca3, and cke at the rising edge of the clock. 2) for lpddr2 sdram, bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. 3) ap ?high? during a read or write command indicates that an auto-precharge will occur to the bank associated with the read or write command. 4) ?x? means ?h or l (but a defined logic level)? 5) self refresh exit and deep power down exit are asynchronous. 6) v ref must be between 0 and vddq during self refresh and deep power down operation. 7) caxr refers to command/address bit ?x? on the rising edge of clock. 8) caxf refers to command/address bit ?x? on the falling edge of clock. 9) cs and cke are sampled at the rising edge of clock. 10) per bank refresh is only allowed in devices with 8 banks. 11) the least-significant column address c0 is not transmitted on the ca bus, and is implied to be zero. 12) ab "high" during precharge command indicates that all bank precharge will occur. in this case, bank address is do-not-care. http:/// - 25 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 6.2 lpddr2-sdram truth tables the truth tables provide complementary information to the stat e diagram, they clarify the device behavior and the applied restr ictions when considering the actual state of all the banks. [table 10] lpddr2-s4 : cke table note : 1) ?cke n ? is the logic state of cke at clock rising edge n; ?cke n-1 ? was the state of cke at the previous clock edge. 2) ?cs ? is the logic state of cs at the clock rising edge n; 3) ?current state? is the state of the lpddr2 device immediately prior to clock edge n. 4) ?command n? is the command registered at clock edge n, and ?operation n? is a result of ?command n?. 5) all states and sequences not shown are illegal or reserv ed unless explicitly described elsewhere in this document. 6) power down exit time (t xp ) should elapse before a command other than nop is issued. 7) self-refresh exit time (t xsr ) should elapse before a command other than nop is issued. 8) the deep power-down exit procedure must be followed as disc ussed in the deep power-down section of the functional descriptio n. 9) the clock must toggle at least once during the t xp period. 10) the clock must toggle at least once during the t xsr time. 11) ' x? means ?don?t care?. 12) upon exiting resetting power down, the device will return to the idle state if tinit5 has expired. device current state *3 cke n-1 *1 cke n *1 cs *2 command n *4 operation n *4 device next state notes active power down l l x x maintain active power down active power down l h h nop exit active power down active 6, 9 idle power down l l x x maintain idle power down idle power down l h h nop exit idle power down idle 6, 9 resetting power down llx x maintain resetting power down resetting power down l h h nop exit resetting power down idle or resetting 6, 9, 12 deep power down llx x maintain deep power down deep power down l h h nop exit deep power down power on 8 self refresh l l x x maintain self refresh self refresh l h h nop exit self refresh idle 7, 10 bank(s) active h l h nop enter active power down active power down all banks idle hlh nop enter idle power down idle power down hll enter self-refresh enter self refresh self refresh hll deep power down enter deep power down deep power down resetting h l h nop enter resetting power down resetting power down h h refer to the command truth table http:/// - 26 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 11] current state bank n - command to bank n note : 1) the table applies when both cken-1 and cken are high, and after t xsr or t xp has been met if the previous state was power down. 2) all states and sequences no t shown are illegal or reserved. 3) current state definitions: - idle: the bank or banks have been precharged, and trp has been met. - active: a row in the bank has been activated, and trcd has been met. no data bursts / accesses and no register accesses are in progress. - reading: a read burst has been initiated, with auto precha rge disabled, and has not yet terminated or been terminated. - writing: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other banks are determined by its current state and figure 11 current state bank n - command to bank n, and according to figure 12 current state bank n - command to bank m. - precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. - row activating: starts with registration of an activate command and ends when trcd is met. once trcd is met, the bank will b e in the ?active? state. - read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when trp has bee n met. once trp has been met, the bank will be in the idle state. - write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been me t. once trp is met, the bank will be in the idle state. 5) the following states must not be interrupted by any executable command; nop commands must be applied to each positive clock edge during these states. - refreshing (per bank): starts with registration of an refres h (per bank) command and ends when trfcpb is met. once trfcpb is met, the bank will be in an ?idle? state. - refreshing (all bank): starts with registration of an refres h (all bank) command and ends when trfcab is met. once trfcab is met, the device will be in an ?all banks idle? state. - idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the idle state. - resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the resetting state. - active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, th e bank will be in the active state. - mr writing: starts with the registration of a mrw command and ends when tmrw has been met. once tmrw has been met, the bank will be in the idle state. - precharging all: starts with the registration of a precharge-a ll command and ends when trp is met. once trp is met, the bank will be in the idle state. 6) bank-specific; requires that the bank is idle and no bursts are in progress. 7) not bank-specific; requires that all banks are idle and no bursts are in progress. 8) not bank-specific reset command is achieved through mode register write command. 9) this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 10) a command other than nop should not be issued to the same ba nk while a read or write burst with auto precharge is enabled. 11) the new read or write command could be auto precharge enabled or auto precharge disabled. 12) a write command may be applied after the completion of the read burst; otherwise, a bst must be used to end the read prior to asserting a write command. 13) not bank-specific. burst terminate (bst) command affects the mo st recent read/write burst started by the most recent read/w rite command, regardless of bank. 14) a read command may be applied after the completion of the write burst; otherwise, a bst must be used to end the write prior to asserting a read command. 15) if a precharge command is issued to a bank in the idle state, trp shall still apply. current state command operation next state notes any nop continue previous operation current state idle activate select and activate row active refresh (per bank) begin to refresh refreshing (per bank) 6 refresh (all bank) begin to refresh refreshing(all bank) 7 mrw load value to mode register mr writing 7 mrr read value from mode register idle mr reading reset begin device auto-initialization resetting 7, 8 precharge deactivate row in bank or banks precharging 9, 15 row active read select column, and start read burst reading write select column, and start write burst writing mrr read value from mode register active mr reading precharge deactivate row in bank or banks precharging 9 reading read select column, and start new read burst reading 10, 11 write select column, and start write burst writing 10, 11, 12 bst read burst terminate active 13 writing write select column, and start new write burst writing 10, 11 read select column, and start read burst reading 10, 11, 14 bst write burst terminate active 13 power on reset begin device auto-initialization resetting 7, 9 resetting mrr read value from mode register resetting mr reading http:/// - 27 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 12] current state bank n - command to bank m note : 1) the table applies when both cken-1 and cken are high, and after t xsr or t xp has been met if the previous state was self refresh or power down. 2) all states and sequences no t shown are illegal or reserved. 3) current state definitions: - idle: the bank has been precharged, and trp has been met. - active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. - reading: a read burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. - writing: a write burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. 4) refresh, self-refresh, and mode register writ e commands may only be issued when all bank are idle. 5) a burst terminate (bst) command cannot be issued to another bank; it applies to the bank represented by the current state on ly. 6) the following states must not be interrupted by any execut able command; nop commands must be applied during each clock cycle while in these states: - idle mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the idle state. - resetting mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the resetting state. - active mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the active state. - mr writing: starts with the registration of a mrw command and ends when t mrw has been met. once t mrw has been met, the bank will be in the idle state. 7) t rrd must be met between activate command to bank n and a subsequent activate command to bank m. 8) reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9) this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 10) mrr is allowed during the row activating state (row activating starts with registration of an activate command and ends whe n t rcd is met.) 11) mrr is allowed during the precharging state. (precharging st arts with registration of a precharge command and ends when t rp is met. 12) not bank-specific; requires that all banks are idle and no bursts are in progress. 13) the next state for bank m depends on the current state of bank m (idle, row activating, precharging, or active). the reader shall note that the state may be in transition when a mrr is issued. therefore, if bank m is in the row ac tivating state and precharging, the next state may be active and pre charge dependent upon t rcd and t rp respec- tively. 14) a write command may be applied after the completion of the read burst, otherwise a bst must be issued to end the read prior to asserting a write command. 15) read with auto precharge enabled and write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in precharge & auto precharge clarific ation on timing spec are followed. 16) a read command may be applied after the completion of the write burst; otherwise, a bst must be issued to end the write pri or to asserting a read command. 17) reset command is achieved through mode register write command. 18) bst is allowed only if a read or write burst is ongoing.data mask truth table. current state of bank n command for bank m operation next state for bank m notes any nop continue previous operation current state of bank m idle any any command allowed to bank m - 18 row activating, active, or precharging activate select and activate row in bank m active 7 read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8 precharge deactivate row in bank or banks precharging 9 mrr read value from mode register idle mr reading or active mr reading 10, 11, 13 bst read or write burst terminate an ongoing read/write from/to bank m active 18 reading (autoprecharge dis- abled) read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8, 14 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing (autoprecharge dis- abled) read select column, and start read burst from bank m reading 8, 16 write select column, and start write burst to bank m writing 8 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 reading with autoprecharge read select column, and start read burst from bank m reading 8, 15 write select column, and start write burst to bank m writing 8, 14, 15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing with autoprecharge read select column, and start read burst from bank m reading 8, 15, 16 write select column, and start write burst to bank m writing 8, 15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 power on reset begin device auto-initialization resetting 12, 17 resetting mrr read value from mode register resetting mr reading http:/// - 28 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 6.3 data mask truth table table 13 dm truth table provi des the data mask truth table. [table 13] dm truth table note : 1) used to mask write data, provided coincident with the corresponding data. name (functional) dm dqs note write enable lvalid1 write inhibit hx1 http:/// - 29 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 7.0 absolute maximum dc ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional opera tion of the device at these or any other conditions above thos e indicated in the operational se ctions of this specif ication is not implied. exposure to abs olute maximum rating condi- tions for extended periods may affect reliability. [table 14] absolute maximum dc ratings note : 1) stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions a bove those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability 2) see ?power-ramp? section in "power-up, initialization, and power-off" on [command definition & timing diagram] for relations hips between power supplies. 3) v refdq 0.6 x vddq; however, v refdq may be vddq provided that v refdq 300mv. 4) v refca 0.6 x vddca; however, v refca may be vddca provided that v refca 300mv. 5) storage temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditi ons, please refer to jesd51-2 standard. parameter symbol min max units notes vdd1 supply voltage relative to vss vdd1 -0.4 2.3 v 2 vdd2 supply voltage relative to vss vdd2 -0.4 1.6 v 2 vddca supply voltage relative to vssca vddca -0.4 1.6 v 2,4 vddq supply voltage relative to vssq vddq -0.4 1.6 v 2,3 voltage on any ball relative to vss vin, vout -0.4 1.6 v storage temperature t stg -55 125 c5 http:/// - 30 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 8.0 ac & dc operating conditions operation or timing that is not specifi ed is illegal, and after such an event, in order to guarantee proper operation, the lpdd r2 device must be powered down and then restarted through the specialized initiali zation sequence before normal operation can continue. 8.1 recommended dc operating conditions [table 15] recommended lpddr2-s4 dc operating conditions note : 1) vdd1 uses significantly less power than vdd2. 8.2 input leakage current [table 16] input leakage current note : 1) the minimum limit requirement is for testing purposes. the leakage current on v refca and v refdq pins should be minimal. 2) although dm is for input only, the dm leakage shall match the dq and dqs/dqs output leakage specification. 8.3 operating temperature range [table 17] operating temperature range note : 1) operating temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement condi tions, please refer to jesd51-2 standard. 2) either the device case temperature rating or the temperatur e sensor (see "temperature sensor" on [command definition & timin g diagram]) may be used to set an appro- priate refresh rate, determine the need for ac timing de-rating and/or monitor the operating temperature. when using the temper ature sensor, the actual device case tempera- ture may be higher than the toper rating that applies for the standard or extended temperature ranges. for example, tcase may b e above 85 o c when the temperature sensor indicates a temperature of less than 85 o c. symbol lpddr2-s4b dram unit min typ max vdd1 1.70 1.80 1.95 core power1 v vdd2 1.14 1.20 1.3 core power2 v vddca 1.14 1.20 1.3 input buffer power v vddq 1.14 1.20 1.3 i/o buffer power v parameter/condition symbol min max unit notes input leakage current for ca, cke, cs , ck, ck any input 0v vin vddca (all other pins not under test = 0v) i l -2 2 ua 2 v ref supply leakage current v refdq = vddq/2 or v refca = vddca/2 (all other pins not under test = 0v) i vref -1 1 ua 1 parameter/condition symbol min max unit standard t oper -25 85 o c http:/// - 31 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.0 ac and dc input measurement levels 9.1 ac and dc logic input levels for single-ended signals 9.1.1 ac and dc input levels for single-ended ca and cs signals [table 18] single-ended ac and dc input levels for ca and cs inputs note : 1) for ca and cs input only pins. v ref = v refca (dc). 2) see overshoot and undershoot specifications on page 42. 3) the ac peak noise on v refca may not allow v refca to deviate from v refca (dc) by more than +/-1% vddca (for reference: approx. +/- 12 mv). 4) for reference: appro x. vddca/2 +/- 12 mv. 9.2 ac and dc input levels for cke [table 19] single-ended ac and dc input levels for cke note : 1) see overshoot and undershoot specifications on page 42. 9.2.1 ac and dc input levels for single-ended data signals [table 20] single-ended ac and dc input levels for dq and dm note : 1)for dq input only pins. vref = v refdq (dc). 2)see overshoot and undershoot specifications on page 42. 3)the ac peak noise on v refdq may not allow v refdq to deviate from v refdq (dc) by more than +/-1% vddq (for reference: approx. +/ - 12 mv). 4)for reference: approx. vddq/2 +/- 12 mv. symbol parameter lpddr2-800 to lpddr2-667 unit notes min max v ihca (ac) ac input logic high vref + 0.220 note 2 v 1, 2 v ilca (ac) ac input logic low note 2 vref - 0.220 v 1, 2 v ihca (dc) dc input logic high vref + 0.130 vddca v 1 v ilca (dc) dc input logic low vssca vref - 0.130 v 1 v refca (dc) reference voltage for ca and cs inputs 0.49 * vddca 0.51 * vddca v 3, 4 symbol parameter min max unit notes v ihcke cke input high level 0.8 * vddca note 1 v 1 v ilcke cke input low level note 1 0.2 * vddca v 1 symbol parameter lpddr2-800 to lpddr2-667 unit notes min max v ihdq (ac) ac input logic high vref + 0.220 note 2 v 1, 2 v ildq (ac) ac input logic low note 2 vref - 0.220 v 1, 2 v ihdq (dc) dc input logic high vref + 0.130 vddq v 1 v ildq (dc) dc input logic low vssq vref - 0.130 v 1 v refdq (dc) reference voltage for dq, dm inputs 0.49 * vddq 0.51 * vddq v 3, 4 http:/// figure 2. illustration of v ref (dc) tolerance and v ref ac-noise limits - 32 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.3 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrated in figure 2 . it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). vdd stands for vddca for v refca and vddq for v refdq . v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). th is average has to meet t he min/max requirements in table 18, single-ended ac and dc input levels for ca and cs inputs . furthermore v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. vref(t) cannot track noise on vddq or vddca if this would send vref outside these specifications. the voltage levels for setup and hold time measurements v ih (ac), v ih (dc), v il (ac) and v il (dc) are dependent on v ref . ?v ref ? shall be understood as v ref (dc), as defined in figure 2 . this clarifies that dc-variations of v ref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. devices will function correctly with appropriate timing deratings with v ref outside these specified levels so long as v ref is maintained between 0.44 x v ddq (or v ddca ) and 0.56 x v ddq (or v ddca ) and so long as the controller achieves the required single-ended ac and dc input levels from instantaneous v ref (see table 18, single-ended ac and dc input levels for ca and cs inputs and table 20, single-ended ac and dc input levels for dq and dm) therefore, system timing and voltage budgets need to account for v ref deviations outside if this range. this also clarifies that the lpddr2 set up/hold specification and derating values need to include time and voltage associated wi th v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (+/-1% of vdd) are included in lpddr2 timings and their associated deratings. vdd vss vdd/2 v ref (dc) v ref ac-noise voltage time v ref (dc) max v ref (dc) min v ref (t) http:/// figure 3. lpddr2-667 to lpddr2-800 input signal - 33 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.4 input signal v ih (ac) v ih (dc) 0.820v 0.730v 0.624v 0.612v 0.600v 0.588v 0.576v 0.470v 0.380v v il (dc) v il (ac) 0.820v 0.730v 0.624v 0.612v 0.600v 0.588v 0.576v 0.470v 0.380v minimum v il and v ih levels 1.200v 0.000v -0.350v v il and v ih levels with ringback 1.550v vdd + 0.35v vdd v ih (ac) v ih (dc) v ref + ac noise v ref + dc error v ref - dc error v ref - ac noise v il (dc) v il (ac) vss vss - 0.35v note : 1) numbers reflect nominal values 2) for ca0-9, ck, ck , and cs , vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 3) for ca0-9, ck, ck , and cs , vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq http:/// - 34 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.5 ac and dc logic input levels for differential signals figure 4. definition of differential ac-swing and ?time above ac-level? t dvac 9.5.1 differential signal definition 9.5.2 differential swing requirements fo r clock (ck - ck) and strobe (dqs - dqs) [table 21] differential ac and dc input levels note : 1)used to define a differential signal slew-rate. 2)for ck - ck use v ih /v il (ac) of ca and v refca ; for dqs - dqs , use v ih /v il (ac) of dqs and v refdq ; if a reduced ac-high or ac-low leve l is used for a signal group, then the reduced level applies also here. 3) these values are not defined, how ever the single-ended signals ck, ck , dqs, and dqs need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations for overshoot and unders hoot. refer to figure 10 overshoot and undershoot definition. 4) for ck and ck , vref = v refca (dc). for dqs and dqs , vref = v refdq (dc). symbol parameter lpddr2-800 to lpddr2-667 unit notes min max v ihdiff (dc) differential input high 2 x (v ih (dc) - vref) note 3 v1 v ildiff (dc) differential input low note 3 2 x (v il (dc) - vref) v 1 v ihdiff (ac) differential input high ac 2 x (v ih (ac) - vref) note 3 v 2 v ildiff (ac) differential input low ac note 3 2 x (v il (ac) - vref) v 2 v ihdiff (ac)min v ihdiff (min) v ihdiff (dc)min v ildiff (dc)max v ildiff (max) v ildiff (ac)max 0.0 ck - ck dqs - dqs half cycle t dvac t dvac http:/// - 35 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 22] allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] tdvac [ps] @ |v ih /ldiff(ac)| = 440mv tdvac [ps] @ |v ih /ldiff(ac)| = 600mv min min > 4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 < 1.0 150 0 http:/// figure 5. single-ended requirement for differential signals. - 36 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.5.3 single-ended requiremen ts for differential signals each individual component of a differential signal (ck, dqs, ck , or dqs ) has also to comply with certai n requirements for single-ended signals. ck and ck shall meet v sel (ac)min / v sel (ac)max in every half-cycle. dqs, dqs shall meet v seh (ac)min / v seh (ac)max in every half-cycle preceedi ng and following a valid transition. note that the applicable ac-levels for ca and dq?s are different per speed-bin. note that while ca and dq signal requirements are with resp ect to vref, the single-ended components of differential signals hav e a requirement with respect to vddq/2 for dqs, dqs and vddca/2 for ck, ck ; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach v sel (ac)max, v seh (ac)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. the single ended requirements for ck, ck , dqs and dqs are found in table 18, single-ended ac and dc input levels for ca and cs inputs and table 20, single-ended ac and dc input levels for dq and dm, respectively. [table 23] single-ended levels for ck, dqs, ck , dqs note : 1) for ck, ck use v seh /v sel (ac) of ca; for strobes (dqs0, dqs0 , dqs1, dqs1 , dqs2, dqs2 , dqs3, dqs3 ) use v ih /v il (ac) of dqs. 2) v ih (ac)/v il (ac) for dqs is based on v refdq ; v seh (ac)/v sel (ac) for ca is based on v refca ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3) these values are not defined, however the single-ended signals ck, ck , dqs0, dqs0 , dqs1, dqs1 , dqs2, dqs2 , dqs3, dqs3 need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. symbol parameter lpddr2-800 to lpddr2-667 unit notes min max v seh (ac) single-ended highlevel for strobes (vddq/2)+0.220 note 3 v 1, 2 single-ended high-level for ck, ck (vddca/2)+0.220 note 3 v 1, 2 v sel (ac) single-ended lowlevel for strobes note 3 (vddq/2)-0.220 v 1, 2 single-ended lowlevel for ck, ck note 3 (vddca/2)-0.220 v 1, 2 vssca or vssq vddca or vddq v sel (ac)max v seh (ac)min v seh (ac) v sel (ac) time vddca/2 or vddq/2 ck, ck dqs or dqs http:/// figure 6. vix definition - 37 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.6 differential input cross point voltage to guarantee tight setup and hold times as well as output skew para meters with respect to clock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in table 23 single-ended levels for ck, dqs, ck, dqs . the differential input cross point voltage v ix is measured from the actual cross point of true and complement signals to the midlevel between of vdd and vss. [table 24] cross point voltage for differential input signals (ck, dqs) note : 1)the typical value of vix(ac) is expected to be about 0.5 v dd of the transmitting device, and vix(ac) is expected to track v ariations in vdd. vix(ac) indicates the voltage at which differential input signals must cross. 2) for ck and ck , vref = v refca (dc). for dqs and dqs , vref = v refdq (dc). symbol parameter lpddr2-800 to lpddr2-667 unit notes min max v ixca differential input cross point voltage relative to vddca/2 for ck, ck - 120 120 mv 1,2 v ixdq differential input cross point voltage relative to vddq/2 for dqs, dqs - 120 120 mv 1,2 vddca or vddq vssca or vssq vddca/2 or vddq/2 v ix v ix v ix ck , dqs ck, dqs http:/// - 38 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 9.7 slew rate definitions for single-ended input signals figure 7. differential input slew rate definition for dqs, dqs and ck, ck see ca and cs setup, hold and derating on page 65. for singl e-ended slew rate definitions for address and command signals. see data setup, hold and slew rate derating on page 71.for single-ended slew rate definitions for data signals. 9.8 slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in table 25 and figure 7. [table 25] differential input slew rate definition note : 1) the differential signal (i.e. ck - ck and dqs - dqs ) must be linear between these thresholds. description measured defined by from to differential input slew rate for rising edge (ck - ck and dqs - dqs ). v ildiffmax v ihdiffmin [v ihdiffmin - v ildiffmax ] / deltatrdiff differential input slew rate for falling edge (ck - ck and dqs - dqs ). v ihdiffmin v ildiffmax [v ihdiffmin - v ildiffmax ] / deltatfdiff delta trdiff delta tfdiff vildiffmax vihdiffmin differential input voltage (i.e.dqs-dqs , ck-ck ) 0 http:/// - 39 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 10.0 ac and dc output measurement levels 10.1 single ended ac and dc output levels table 26 shows the output levels used for measurements of single ended signals. [table 26] single-ended ac and dc output levels note : 1) ioh = -0.1ma. 2) iol = 0.1ma. 10.2 differential ac and dc output levels table 27 shows the output levels used for measurements of differential signals (dqs, dqs ). [table 27] differential ac and dc output levels note : 1) ioh = -0.1ma. 2) iol = 0.1ma. symbol parameter lpddr2-800 to lpddr2-667 unit notes v oh (dc) dc output high measurement level (for iv curve linearity) 0.9 x v ddq v1 v ol (dc) dc output low measurement level (for iv curve linearity) 0.1 x v ddq v2 v oh (ac) dc output high measurement level (for iv curve linearity) v ref + 0.12 v v ol (ac) dc output low measurement level (for iv curve linearity) v ref - 0.12 v i oz output leakage current (dq, dm, dqs, dqs ) (dqs are disabled; 0v vout vddq min -5 ua max 5 ua mm pupd delta ron between pull-up and pull-down for dq/dm min -15 % max 15 % symbol parameter lpddr2-800 to lpddr2-667 unit notes v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.20 x v ddq v v oldiff (ac) ac differential output low measurement level (for output sr) - 0.20 x v ddq v http:/// figure 8. single ended output slew rate definition - 40 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 10.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol (ac) and v oh (ac) for single ended signals as shown in table 28 and figure 8 . [table 28] single-ended output slew rate definition note : 1) output slew rate is verified by design and characterization, and may not be subject to production test. [table 29] output slew rate (single-ended) note : 1) measured with output reference load. 2) the ratio of pull-up to pull-down slew rate is specified fo r the same temperature and voltage, over the entire temperature a nd voltage range. for a given output, it represents the maximum difference between pull-up and pulldown drivers due to process variation. 3) the output slew rate for falling and rising ed ges is defined and measured between vol(dc) and voh(dc). 4) slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logichigh and 1/2 of dq si gnals per data byte driving logic-low. description measured defined by from to single-ended output slew rate for rising edge v ol (ac) v oh (ac) [v oh (ac) - v ol (ac)] / deltatrse single-ended output slew rate for falling edge v oh (ac) v ol (ac) [v oh (ac) - v ol (ac)] / deltatfse lpddr2-800 to lpddr2-667 units parameter symbol min max single-ended output slew rate (ron = 40 : +/- 30%) srqse 1.5 3.5 v/ns single-ended output slew rate (ron = 60 : +/- 30%) srqse 1.0 2.5 v/ns output slew-rate matching ratio (pull-up to pull-down) 0.7 1.4 description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals delta trse delta tfse v ol(ac) v oh(ac) single ended output voltage(i.e dq) v tt http:/// figure 9. differential output slew rate definition - 41 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 10.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and voh- diff(ac) for differential signals as shown in table 30 and figure 9 . [table 30] differential output slew rate definition note : 1) g output slew rate is verified by design and characterization, and may not be subject to production test. [table 31] differential output slew rate note : 1) measured with output reference load. 2) the output slew rate for falling and rising ed ges is defined and measured between vol(ac) and voh(ac). 3) slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logichigh and 1/2 of dq si gnals per data byte driving logic-low. description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) [v ohdiff (ac) - v oldiff (ac)] / deltatrdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) [v ohdiff (ac) - v oldiff (ac)] / deltatfdiff lpddr2-800 to lpddr2-667 units parameter symbol min max differential output slew rate (ron = 40 : +/- 30%) srqdiff 3.0 7.0 v/ns differential output slew rate (ron = 60 : +/- 30%) srqdiff 2.0 5.0 v/ns description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differential signals delta trdiff delta tfdiff v ol(ac) v oh(ac) differential output voltage (i.e dqs-dqs ) 0 http:/// figure 10. overshoot and undershoot definition - 42 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 10.5 overshoot and undershoot specifications [table 32] ac overshoot/undershoot specification note : 1) for ca0-9, ck, ck , cs , and cke, vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 2) for ca0-9, ck, ck , cs , and cke, vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq. 3) values are referenced from actual vddq, vddca, vssq, and vssca levels. note : 1) for ca0-9, ck, ck , cs , and cke, vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 2) for ca0-9, ck, ck , cs , and cke, vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq. parameter 800 667 units maximum peak amplitude allowed for overshoot area. (see figure 10 ) max 0.35 v maximum peak amplitude allowed for undershoot area. (see figure 10 ) max 0.35 v maximum area above vdd. (see figure 10 ) max 0.20 0.24 v-ns maximum area below vss. (see figure 10 ) max 0.20 0.24 v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) time (ns) http:/// - 43 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 11.0 output buffer characteristics figure 11. hsul_12 driver output reference load for timing and slew rate 11.1 hsul_12 driver output timing reference load these ?timing reference loads? are not intended as a precise repres entation of any particular system environment or a depiction of the actual load pre- sented by a production tester. system designers should use ibis or other simulation tool s to correlate the timing reference loa d to a system environment. manufacturers correlate to their production test conditions, generally one or more coax ial transmission lines terminated at the tester electronics. note : 1) all output timing parameter values (like t dqsck , t dqsq , t qhs, t hz , t rpre etc.) are reported with respect to this reference load . this reference load is also used to report slew rate. output vref lpddr2 0.5 x vddq sdram cload = 5pf rtt = 50 : vtt = 0.5 x vddq http:/// figure 12. output driver: definition of voltages and currents - 44 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 12.0 ron pu and ron pd resistor definition note : 1)this is under the condition that ron pd is turned off. note : 1) this is under the condition that ron pu is turned off. y v u w | } k k x } ? ? ? ? h i z p ? ? ? --------------- --------------- ------------- - = y v u w k } ? ? ? h i z p ? ? ? ----------------------------- - = vddq vssq dq ron pu ron pd to other circuitry like rcv, ... chip in drive mode output driver v out i out i pu i pd http:/// - 45 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 12.1 ron pu and ron pd characteristics with zq calibration output driver impedance ron is defined by the value of t he external reference resistor rzq. nominal rzq is 240 [table 33] output driver dc electrical characteristics with zq calibration note : 1) across entire operating temperature range, after calibration. 2) rzq = 240 . 3) the tolerance limits are specified after calibration with stable voltage and temperature. for behavior of the tolerance limi ts if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 4) pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. 5) mesaurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ro npd, both at 0.5 x vddq: for example, with mmpupd(max) = 15% and ronpd = 0.85, ronpu must be less than 1.0 12.2 output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tole rance limits widen according to the tables shown below. [table 34] output driver sensitivity definition note : 1) (@ calibration), (@ calibration) 2) drondt and drondv are not s ubject to production test but are ve rified by design and characterization. [table 35] output driver temperature and voltage sensitivity ron nom resistor vout min nom max unit notes 34.3 ron34pd 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 ron34pu 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 40.0 ron40pd 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 ron40pu 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 48.0 ron48pd 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 ron48pu 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 60.0 ron60pd 0.5 x vddq 0.85 1.00 1.15 rzq/4 1,2,3,4 ron60pu 0.5 x vddq 0.85 1.00 1.15 rzq/4 1,2,3,4 80.0 ron80pd 0.5 x vddq 0.85 1.00 1.15 rzq/3 1,2,3,4 ron80pu 0.5 x vddq 0.85 1.00 1.15 rzq/3 1,2,3,4 120.0 ron120pd 0.5 x vddq 0.85 1.00 1.15 rzq/2 1,2,3,4 ron120pu 0.5 x vddq 0.85 1.00 1.15 rzq/2 1,2,3,4 mismatch between pull-up and pull-down mmpupd -15.00 +15.00 % 1,2,3,4,5 resistor vout min max unit notes ronpd 0.5 x vddq % 1,2 ronpu symbol parameter min max unit notes drondt ron temperature sensitivity 0.00 0.75 % / c drondv ron voltage sensitivity 0.00 0.20 % / mv mmpupd ronpu ronpd ronnom 100 85 drondt t () drondv v () 115 drondt t () drondv v () t tt v vv http:/// - 46 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 12.3 ron pu and ron pd characteristics without zq calibration output driver impedance ron is defined by design and characterization as default setting. [table 36] output driver dc electrical characteristics without zq calibration note: 1) across entire operating temperature range, without calibration. ron nom resistor vout min nom max unit notes 34.3 ron34pd 0.5 x vddq 24 34.3 44.6 1 ron34pu 0.5 x vddq 24 34.3 44.6 1 40.0 ron40pd 0.5 x vddq 28 40 52 1 ron40pu 0.5 x vddq 28 40 52 1 48.0 ron48pd 0.5 x vddq 33.6 48 62.4 1 ron48pu 0.5 x vddq 33.6 48 62.4 1 60.0 ron60pd 0.5 x vddq 42 60 78 1 ron60pu 0.5 x vddq 42 60 78 1 80.0 ron80pd 0.5 x vddq 56 80 104 1 ron80pu 0.5 x vddq 56 80 104 1 120.0 ron120pd 0.5 x vddq 84 120 156 1 ron120pu 0.5 x vddq 84 120 156 1 http:/// - 47 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 12.4 rzq i-v curve [table 37] rzq i-v curve voltage[v] ron = 240 (rzq) pull-down pull-up current [ma] / ron [ohms] current [ma] / ron [ohms] default value after zqreset with calibration default value after zqreset with calibration min max min max min max min max [ma] [ma] [ma] [ma] [ma] [ma] [ma] [ma] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26 0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53 0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78 0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04 0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29 0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53 0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79 0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03 0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26 0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49 0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72 0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94 0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15 0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36 0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55 0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74 0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91 0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05 0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23 1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33 1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44 1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52 1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59 1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65 http:/// figure 14. ron = 240 ohms g iv curve after calibration figure 13. ron = 240 ohms iv curve after zqreset - 48 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 \ 6 \ 4 \ 2 0 2 4 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 pd ? in \ fab ? mi n pd ? in \ fab ? max pu ? in \ fab ? mi n pu ? in \ fab ? max vo l t a g e ma \ 6 \ 4 \ 2 0 2 4 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 pd ? cal \ mi n pd ? cal \ max pu ? cal \ mi n pu ? cal \ max voltage ma http:/// - 49 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 13.0 input/output capacitance [table 38] input/output capacitance (t oper ; v ddq = 1.14-1.3v; v ddca = 1.14-1.3v; v dd1 = 1.7-1.95v,lpddr2-s4b v dd2 = 1.14-1.3v) note : 1) this parameter applies to both die and package. 2) this parameter is not subject to production test. it is ve rified by design and characterizati on. the capacitance is measured according to jep147 (procedure for measuring input capacitance using a vector network analyzer (vna) with vd d1, vdd2, vddq, vss, vssca, vssq applied and all other pins floa ting. 3) absolute value of cck - cck . 4) ci applies to cs , cke, ca0-ca9. 5) cdi = ci - 0.5 * (cck + cck ) 6) dm loading matches dq and dqs. 7) mr3 i/o configuration ds op3-op0 = 0001b (34.3 ohm typical) 8) absolute value of cdqs and cdqs . 9) cdio = cio - 0.5 * (cdqs + cdqs ) in byte-lane. 10) cdi2 = ci2 - 0.25 * (cck_t + cck_c) parameter symbol lpddr2 800-667 units notes input capacitance, ck and ck cck min 2.0 pf 1,2 max 5.0 pf 1,2 input capacitance delta, ck and ck cdck min 0.0 pf 1,2,3 max 0.40 pf 1,2,3 cin, all other input-only pins except cs and cke ci1 min 2.0 pf 1,2,4 max 5.0 pf 1,2,4 cin, cs 0 / cs 1 and cke0 / cke1 ci2 min 1.0 pf 1,2,4 max 3.0 pf 1,2,4 cdelta, all other input-only pins except cs and cke cdi1 min -1.0 pf 1,2,5 max 1.0 pf 1,2,5 cdelta, cs 0 / cs 1 and cke0 / cke1 cdi2 min -1.0 pf 1,2,5,10 max 1.0 pf 1,2,5,10 input/output capacitance, dq, dm, dqs, dqs cio min 2.5 pf 1,2,6,7 max 6 pf 1,2,6,7 input/output capacitance delta, dqs, dqs cddqs min 0.0 pf 1,2,7,8 max 0.50 pf 1,2,7,8 input/output capacitance delta, dq, dm cdio min -1.0 pf 1,2,7,9 max 1.0 pf 1,2,7,9 input/output capacitance zq pin czq min 0.0 pf 1,2 max 6.0 pf 1,2 http:/// - 50 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 14.0 idd specification parameters and test conditions 14.1 idd measurement conditions the following definitions are used within the idd measurement tables: low: v in v il (dc) max high: v in v ih (dc) min stable: inputs are stable at a high or low level switching: see table 39 and table 40 . [table 39] definition of switching for ca input signals note : 1) cs must always be driven high. 2) 50% of ca bus is changing between hi gh and low once per clock for the ca bus. 3) the above pattern (n, n+1, n+2, n+3...) is used continuously during idd measurement for idd values that require switching on the ca bus. [table 40] definition of switching for idd4r note : 1) data strobe (dqs) is changing between high and low every clock cycle. 2) the above pattern (n, n+1...) is used continuously during idd measurement for idd4r. switching for ca ck (rising) / ck (falling) ck (falling) / ck (rising) ck (rising) / ck (falling) ck (falling) / ck (rising) ck (rising) / ck (falling) ck (falling) / ck (rising) ck (rising) / ck (falling) ck (falling) / ck (rising) cycle n n+1 n+2 n+3 cs high high high high ca0 high low low low low high high high ca1 high high high low low low low high ca2 high low low low low high high high ca3 high high high low low low low high ca4 high low low low low high high high ca5 high high high low low low low high ca6 high low low low low high high high ca7 high high high low low low low high ca8 high low low low low high high high ca9 high high high low low low low high clock cke cs clock cycle number command ca0-ca2 ca3-ca9 all dq rising high low n read_rising hlh lhlhlhl l falling high low n read_falling lll lllllll l rising high high n + 1 nop lll lllllll h falling high high n + 1 nop hlh hlhllhl l rising high low n + 2 read_rising hlh hlhllhl h falling high low n + 2 read_falling hhh hhhhhhh h rising high high n + 3 nop hhh hhhhhhh h falling high high n + 3 nop hlh lhlhlhl l http:/// - 51 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 41] definition of switching for idd4w note : 1) data strobe (dqs) is changing between high and low every clock cycle. 2) data masking (dm) must always be driven low. 3) the above pattern (n, n+1...) is used c ontinuously during idd measurement for idd4w. 14.2 idd specifications idd values are for the entire operating voltage range and the standard and extended temperature ranges, unless otherwise noted. [table 42] lpddr2 idd specification parameters and operating conditions clock cke cs clock cycle number command ca0-ca2 ca3-ca9 all dq rising high low n write_rising hll lhlhlhl l falling high low n write_falling lll lllllll l rising high high n + 1 nop lll lllllll h falling high high n + 1 nop hlh hlhllhl l rising high low n + 2 write_rising hll hlhllhl h falling high low n + 2 write_falling hhh hhhhhhh h rising high high n + 3 nop hhh hhhhhhh h falling high high n + 3 nop hlh lhlhlhl l parameter/condition symbol power supply units notes operating one bank active-precharge current t ck = t ck(avg)min ; t rc = t rcmin ; cke is high; cs is high between valid commands; address bus inputs are switching; data bus inputs are stable idd0 1 vdd1 ma 3,14 idd0 2 vdd2 ma 3,14 idd0 in vddca + vddq ma 3,4,14 idle power-down standby current: t ck = t ck(avg)min ; cke is low; cs is high; all banks idle; address bus inputs are switching; data bus inputs are stable idd2p 1 vdd1 ma 3,13 idd2p 2 vdd2 ma 3,13 idd2p in vddca + vddq ma 3,4,13 idle power-down standby current with clock stop: ck =low, ck =high; cke is low; cs is high; all banks idle; address bus inputs are switching; data bus inputs are stable idd2ps 1 vdd1 ma 3,13 idd2ps 2 vdd2 ma 3,13 idd2ps in vddca + vddq ma 3,4,13 idle non power-down standby current: t ck = t ck(avg)min ; cke is high; cs is high; all banks idle; address bus inputs are switching; data bus inputs are stable idd2n 1 vdd1 ma 3,14 idd2n 2 vdd2 ma 3,14 idd2n in vddca + vddq ma 3,4,14 idle non power-down standby current with clock stop: ck=low, ck =high; cke is high; cs is high; all banks idle; ca bus inputs are switching; data bus inputs are stable idd2ns 1 vdd1 ma 3,14 idd2ns 2 vdd2 ma 3,14 idd2ns in vddca + vddq ma 3,4,14 http:/// - 52 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 active power-down standby current: t ck = t ck(avg)min ; cke is low; cs is high; one bank active; address bus inputs are switching; data bus inputs are stable idd3p 1 vdd1 ma 3,14 idd3p 2 vdd2 ma 3,14 idd3p in vddca + vddq ma 3,4,14 active power-down standby current with clock stop: ck=low, ck =high; cke is low; cs is high; one bank active; address bus inputs are switching; data bus inputs are stable idd3ps 1 vdd1 ma 3,14 idd3ps 2 vdd2 ma 3,14 idd3ps in vddca + vddq ma 3,4,14 active non power-down standby current: t ck = t ck(avg)min ; cke is high; cs is high; one bank active; address bus inputs are switching; data bus inputs are stable idd3n 1 vdd1 ma 3,14 idd3n 2 vdd2 ma 3,14 idd3n in vddca + vddq ma 3,4,14 active non power-down standby current with clock stop: ck=low, ck =high; cke is high; cs is high; one bank active; ca bus inputs are switching; data bus inputs are stable idd3ns 1 vdd1 ma 3,14 idd3ns 2 vdd2 ma 3,14 idd3ns in vddca + vddq ma 3,4,14 operating burst read current: t ck = t ck(avg)min ; cs is high between valid commands; one bank active; bl = 4; rl = rlmin; address bus inputs are switching; 50% data change each burst transfer idd4r 1 vdd1 ma 3,14 idd4r 2 vdd2 ma 3,14 idd4r in vddca ma 3,14 idd4r q vddq ma 3,6,14 operating burst write current: t ck = t ck(avg)min ; cs is high between valid commands; one bank active; bl = 4; wl = wlmin; address bus inputs are switching; 50% data change each burst transfer idd4w 1 vdd1 ma 3,14 idd4w 2 vdd2 ma 3,14 idd4w in vddca + vddq ma 3,4,14 all bank refresh burst current: t ck = t ck(avg)min ; cke is high between valid commands; t rc = t rfcabmin ; burst refresh; address bus inputs are switching; data bus inputs are stable; idd5 1 vdd1 ma 3,14 idd5 2 vdd2 ma 3,14 idd5 in vddca + vddq ma 3,4,14 all bank refresh average current: t ck = t ck(avg)min ; cke is high between valid commands; t rc = t refi ; address bus inputs are switching; data bus inputs are stable; idd5ab 1 vdd1 ma 3,14 idd5ab 2 vdd2 ma 3,14 idd5ab in vddca + vddq ma 3,4,14 per bank refresh average current: t ck = t ck(avg)min ; cke is high between valid commands; t rc = t refi /8; address bus inputs are switching; data bus inputs are stable; idd5pb 1 vdd1 ma 1,3,14 idd5pb 2 vdd2 ma 1,3,14 idd5pb in vddca + vddq ma 1,3,4,14 parameter/condition symbol power supply units notes http:/// - 53 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 note : 1) per bank refresh only applicable for lpddr2-s4 devices of 1g b or higher densities and lpddr2-s2 devices of 4gb and higher de nsities. 2) this is the general definition that applies to full array self refresh. refer to table 44, idd6 partial array self-refresh c urrent for details of partial array self refresh idd6 specification. 3) idd values published are the maximum of the distribution of the arithmetic mean. 4) measured currents are the summation of vddq and vddca. 5) to calculate total current consumption, the curr ents of all active operations must be considered. 6) guaranteed by design with output load of 5pf and ron = 40ohm. 7) idd current specifications are tested after the device is properly initialized. 8) in addition, supplier data sheets may include additional self refresh idd values for temperature subranges within the standa rd or extended temperature ranges. 9) 1x self-refresh rate is the rate at which the lpddr2-s4 devic e is refreshed internally during self-refresh in the standard t emperature range. 10) idd6 85 c is guaranteed, idd6 45 c is typical values. 11) idd8 85 c is guaranteed, idd8 45 c is typical values. 12) dpd (deep power down) function is an optional feature, and it will be enabled upon request. please contact samsung for more information. 13) these specification values are under same condition of the both chips selected at the same time. 14) these specification values are under i dd2ps condition of the other unselected chip. self refresh current (standard temperature range): ck=low, ck =high; cke is low; address bus inputs are stable; data bus inputs are stable; maximum 1x self-refresh rate; idd6 1 vdd1 ma 2,3,8,9,10,13 idd6 2 vdd2 ma 2,3,8,9,10,13 idd6 in vddca + vddq ma 2,3,4,8,9,10, 13 deep power-down current: address bus inputs are stable; data bus inputs are stable; idd8 1 vdd1 ua 3,11, 12,13 idd8 2 vdd2 ua 3,11, 12,13 idd8 in vddca + vddq ua 3,4,11, 12,13 parameter/condition symbol power supply units notes http:/// - 54 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 14.3 idd spec table [table 43] idd specification for 4gb ddp lpddr2-s4b 2/cs, 2cke symbol power supply vdd2=1.2v (s4b) units notes 128m x32 (K4P4G304EC) 800mbps 667mbps idd0 idd0 1 vdd1 6.3 6.3 ma 3,14 idd0 2 vdd2 40.8 40.8 ma 3,14 idd0 in vddca + vddq 5.1 5.1 ma 3,4,14 idd2p idd2p 1 vdd1 0.6 0.6 ma 3,13 idd2p 2 vdd2 1.6 1.6 ma 3,13 idd2p in vddca + vddq 0.2 0.2 ma 3,4,13 idd2ps idd2ps 1 vdd1 0.6 0.6 ma 3,13 idd2ps 2 vdd2 1.6 1.6 ma 3,13 idd2ps in vddca + vddq 0.2 0.2 ma 3,4,13 idd2n idd2n 1 vdd1 1.3 1.3 ma 3,14 idd2n 2 vdd2 8.8 8.3 ma 3,14 idd2n in vddca + vddq 5.1 5.1 ma 3,4,14 idd2ns idd2ns 1 vdd1 1.3 1.3 ma 3,14 idd2ns 2 vdd2 4.8 4.3 ma 3,14 idd2ns in vddca + vddq 5.1 5.1 ma 3,4,14 idd3p idd3p 1 vdd1 2.3 2.3 ma 3,14 idd3p 2 vdd2 3.8 3.8 ma 3,14 idd3p in vddca + vddq 0.2 0.2 ma 3,4,14 idd3ps idd3ps 1 vdd1 2.3 2.3 ma 3,14 idd3ps 2 vdd2 3.8 3.8 ma 3,14 idd3ps in vddca + vddq 0.2 0.2 ma 3,4,14 idd3n idd3n 1 vdd1 2.3 2.3 ma 3,14 idd3n 2 vdd2 12.8 12.3 ma 3,14 idd3n in vddca + vddq 5.1 5.1 ma 3,4,14 idd3ns idd3ns 1 vdd1 2.3 2.3 ma 3,14 idd3ns 2 vdd2 6.8 6.3 ma 3,14 idd3ns in vddca + vddq 5.1 5.1 ma 3,4,14 idd4r idd4r 1 vdd1 2.3 2.3 ma 3,14 idd4r 2 vdd2 130.8 120.8 ma 3,14 idd4r in vddca 5.05 5.05 ma 3,14 idd4r q vddq 110.05 100.05 ma 3,6,14 idd4w idd4w 1 vdd1 2.3 2.3 ma 3,14 idd4w 2 vdd2 140.8 130.8 ma 3,14 idd4w in vddca + vddq 13.1 13.1 ma 3,4,14 http:/// - 55 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 note : 1) see table 42, lpddr2 idd specification parameters and operating conditions for notes. [table 44] idd6 partial array self-refresh current note : 1) idd6 85 c is the maximum and idd6 45 c is typical of the distribution of the arithmetic mean. idd5 idd5 1 vdd1 10.3 10.3 ma 3,14 idd5 2 vdd2 100.8 100.8 ma 3,14 idd5 in vddca + vddq 5.1 5.1 ma 3,4,14 idd5ab idd5ab 1 vdd1 2.3 2.3 ma 3,14 idd5ab 2 vdd2 10.8 10.8 ma 3,14 idd5ab in vddca + vddq 5.1 5.1 ma 3,4,14 idd5pb idd5pb 1 vdd1 2.3 2.3 ma 1,3,14 idd5pb 2 vdd2 20.8 20.8 ma 1,3,14 idd5pb in vddca + vddq 5.1 5.1 ma 1,3,4,14 idd6 idd6 1 45 c vdd1 0.24 0.24 ma 2,3,8,9,10,13 85 c1.01.0 idd6 2 45 c vdd2 0.9 0.9 ma 2,3,8,9,10,13 85 c3.43.4 idd6 in 45 c vddca + vddq 0.1 0.1 ma 2,3,4,8,9,10,1 3 85 c0.20.2 idd8 idd8 1 45 c vdd1 10 10 ua 3,11,12 ,13 85 c4040 idd8 2 45 c vdd2 20 20 ua 3,11,12 ,13 85 c 100 100 idd8 in 45 c vddca + vddq 10 10 ua 3,4,11,12 ,13 85 c6060 parameter 4gb ddp 2/cs, 2cke unit lpddr2-s4b 45 c 85 c idd6 partial array self-refresh current (max) full array vdd1 240 1000 ua vdd2 900 3400 vddca + vddq 100 200 1/2 array vdd1 200 700 ua vdd2 560 2000 vddca + vddq 100 200 1/4 array vdd1 180 600 ua vdd2 380 1400 vddca + vddq 100 200 1/8 array vdd1 160 500 ua vdd2 300 1200 vddca + vddq 100 200 symbol power supply vdd2=1.2v (s4b) units notes 128m x32 (K4P4G304EC) 800mbps 667mbps http:/// - 56 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.0 electrical characteristics and ac timing 15.1 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input cl ocks violating the min/max values may result i n malfunction of the lpddr2 device. 15.1.1 definition for tck(avg) and nck tck(avg) is calculated as the average cl ock period across any consec utive 200 cycle window, where eac h clock period is calculat ed from rising edge to rising edge. unit ?tck(avg)? represents the actual cl ock average tck(avg) of the input clock under operation. unit ?nck? represents one cloc k cycle of the input clock, counting the actual clock edges. tck(avg) may change by up to +/-1% within a 100 clock cycl e window, provided that all jitte r and timing specs are met. 15.1.2 definition for tck(abs) t ck (abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. t ck (abs) is not subject to produc- tion test. 15.1.3 definition for tch(avg) and tcl(avg) t ch (avg) is defined as the average high pulse width, as calculated across any cons ecutive 200 high pulses. t cl (avg) is defined as the average low pulse width, as calculated across any co nsecutive 200 low pulses. 15.1.4 definition for tjit(per) t jit (per) is the single period jitter defined as the la rgest deviation of any signal tck from tck(avg). t jit (per) = min/max of {tck i - tck(avg) where i = 1 to 200}. t jit (per),act is the actual cloc k jitter for a given system. t jit (per),allowed is the specifi ed allowed clock period jitter. t jit (per) is not subject to production test. tck avg () tck j j 1 n ?? ?? ?? ?? n ? where n 200 tch avg () tch j j 1 n ?? ?? ?? ?? ntckavg () () ? where n 200 tcl avg () tcl j j 1 n ?? ?? ?? ?? ntckavg () () ? where n 200 http:/// - 57 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.1.5 definition for tjit(cc) tjit(cc) is defined as the absolute difference in clock peri od between two consecut ive clock cycles. t jit (cc) = max of |{tck i +1 - tck i }|. t jit (cc) defines the cyc le to cycle jitter. t jit (cc) is not subject to production test. 15.1.6 definition for terr(nper) t err (nper) is defined as the cumulative error across n multiple consecutive cycles from tck(avg). t err (nper),act is the actual clock jitter over n cycl es for a given system. t err (nper),allowed is the specified allow ed clock period jitter over n cycles. t err (nper) is not subject to production test. t err (nper),min can be calculated by the formula shown below: t err (nper),max can be calculated by the formula shown below using these equations, t err (nper) tables can be generated for each t jit (per),act value. 15.1.7 definition for duty cycle jitter tjit(duty) t jit (duty) is defined with absolute and average specification of tch / tcl. 15.1.8 definition for tck(abs), tch(abs) and tcl(abs) these parameters are specified per their average values, however it is understood that the following relationship between the a verage timing and the absolute instantaneous timi ng holds at all times [table 45] definition for tck(abs), tch(abs), and tcl(abs) note : 1) tck(avg),min is expressed as ps for this table. 2) tjit(duty),min is a negative value. paramter symbol min unit absolute clock period tck(abs) tck(avg).min + tjit(per).min ps absolute clock high pulse width t ch (abs) tch(avg),min + tjit(duty),min / tck(avg)min tck(avg) absolute clock low pulse width t cl (abs) tcl(avg),min + tjit(duty),m in / tck(avg)min tck(avg) terr nper () tck j ji in 1 ?? ?? ?? ?? ntckavg () terr nper () min , 10.68 ln n () () tjit per () min , terr nper () max , 10.68 ln n () () tjit per () max , tjit duty () min , min tch abs () min tch avg () min , , () tcl abs () min tcl avg () min , , () , () tck avg () tjit duty () max , max tch abs () max tch avg () max , , () tcl abs () max tcl avg () max , , () , ( ) tck avg () http:/// - 58 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.2 period clock jitter lpddr2 devices can tolerate some clock per iod jitter without core timing parameter de- rating. this section describes device tim ing requirements in the presence of clock period jitter (tjit(per)) in excess of the values found in table 47, lpddr2 ac timing table and how to determine cycle time de-rating and clock cycle de-rating. 15.2.1 clock period jitter effects on core timing parameters (trcd, trp, trtp, twr, twra, twtr, trc, tras, trrd, tfaw ) core timing parameters extend across multiple clock cycles. period clock jitter will im pact these parameters when measured in n umbers of clock cycles. when the device is operated with clock jitte r within the specification limits, the lpddr2 device is characterized and verified to support tnparam = ru{tparam / tck(avg)}. when the device is operated with clock jitter outside specification limits, the number of clocks or tck(avg) may need to be inc reased based on the values for each core timing parameter. note : 1) tfaw is only applied in devices with 8 banks. 15.2.1.1 cycle time de-rating for core timing parameters for a given number of clocks (tnparam), for each core timing para meter, average clock period (tck(avg)) and actual cumulative p eriod error (terr(tnparam),act) in excess of the allowed cumulative peri od error (terr(tnparam),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter (tcore). a cycle time derating analys is should be conducted for each core timing paramete r. the amount of cycle time derating required i s the maximum of the cycle time de-ratings determined for each individual core timing parameter. 15.2.1.2 clock cycle de-rating for core timing parameters for a given number of clocks (tnparam) for each core timing parameter, clock cycle de-rating should be specif ied with amount of period jitter (tjit(per)). for a given number of clocks (tnparam), for each core timing para meter, average clock period (tck(avg)) and actual cumulative p eriod error (terr(tnparam),act) in excess of the allowed cumulative period error (terr(tnparam),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a posi tive value for a core timing parameter (tcore). a clock cycle de-rating analys is should be conducted for eac h core timing parameter. 15.2.2 clock jitter effects on co mmand/address timing parameters (tis, tih, tiscke, tihcke, tisb, tihb, tisckeb, tihckeb) these parameters are measured from a command/address signal (cke, cs, ca0 - ca9) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per)), as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of cl ock jitter values, these values shall be met. cycletimederating max tparam terr tnparam () act terr tnparam () allowed , , tnparam tck avg () ? ? ? ? 0 , ? ? ? ? ? ? clockcyclederating ru tparam terr tnparam () act terr tnparam () allowed , , tck avg () ?? ?? ?? tnparam http:/// - 59 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.2.3 clock jitter effect s on read timing parameters 15.2.3.1 trpre when the device is operated with input cloc k jitter, trpre needs to be de-rated by the actual period jitter (tjit(per),act,max) of the input clock in excess of the allowed period jitter (tjit(per),allowed,max). ou tput de-ratings are relative to the input clock. for example, if the measured jitter into a lpddr2-800 device has tck(avg) = 2500 ps, tjit(per),ac t,min = -172 ps and tjit(per),act,max= + 19 3 ps, then trpre,min,derated = 0.9 - (tjit(per),act,max - tjit(per),allowed,max)/tck(avg) = 0.9 - (193 - 100)/2500= .8628 tck(avg) 15.2.3.2 tlz(dq), thz(dq), tdqsck, tlz(dqs), thz(dqs) these parameters are measured from a spec ific clock edge to a data signal (dmn, dqm.: n=0,1,2,3. m=0 ?31) transition and will b e met with respect to that clock edge. therefore, they are not affected by the amount of clock jitte r applied (i.e. tjit(per). 15.2.3.3 tqsh, tqsl these parameters are affected by duty cycle jitter which is re presented by tch(abs)min and tcl(abs )min. therefore tqsh(abs)min and tqsl(abs)min can be specified with t ch(abs)min and tcl(abs)min. tqsh(abs)min = tch(abs)min ? 0.05 tqsl(abs)min = tcl(abs)min ? 0.05 these parameters determine absolute data -valid window at the lpddr2 device pin. absolute min data-valid window @lpddr2 device pin = min { ( tqsh(abs)min * tck(avg)min ? td qsqmax ? tqhsmax ) , ( tqsl(abs)min * tck(avg)min ? tdqsqmax ? tqhsmax ) } this minimum data-valid window shall be met at the target frequency regardless of clock jitter. 15.2.3.4 trpst trpst is affected by duty cycle jitter wh ich is represented by tcl(abs). therefore tr pst(abs)min can be specified by tcl(abs)mi n. trpst(abs)min = tcl(abs)min ? 0.05 = tqsl(abs)min 15.2.4 clock jitter effects on write timing parameters 15.2.4.1 tds, tdh these parameters are measured from a data signal (dmn, dqm.: n=0, 1,2,3. m=0 ?31) transition edge to its respective data strobe signal (dqsn, dqs n : n=0,1,2,3) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), as the setup and h old are relative to the clock sig- nal crossing that latches the command/ address. regardless of clock jitter values, these values shall be met. 15.2.4.2 tdss, tdsh these parameters are measured from a data strobe signal (dqsx, dqs x) crossing to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitte r applied (i.e. tjit(per)), as the setup and hold are relative to the clock signal cro ssing that latches the command/ address. regardless of clock jitter values, these values shall be met. trpre min derated , () 0.9 tjit per () act max , tjit per () allowed max tck avg () ?? ?? http:/// - 60 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.2.4.3 tdqss this parameter is measured from a data strobe signal (dqsx, dqsx ) crossing to the subs equent clock signal (ck/ck ) crossing. when the device is oper- ated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tjit(per),act of the input clock in excess of the allowed period jit- ter tjit(per),allowed. for example, if the measured jitter into a lpddr2-800 device has tck(avg)= 2500 ps, tjit(per),act,min = -172 ps and tjit(per),act,max= + 19 3 ps, then tdqss,(min,derated) = 0.75 - (tjit(per),ac t,min - tjit(per),allowed,min)/tck(avg) = 0.75 - (-172 + 100)/2500 = .7788 tck(avg) and tdqss,(max,derated) = 1.25 - (tjit(per),act,max - tjit(per), allowed,max)/tck(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tck(avg) 15.3 lpddr2-s4 refresh requirement per device density [table 46] lpddr2-s4 refresh requirement parameters (per density) parameter symbol 2 gb unit number of banks 8 refresh window tcase 85 c t refw 32 ms required number of refresh commands (min) r 8,192 average time between refresh commands (for reference only) tcase 85 c refab t refi 3.9 us refpb t refipb 0.4875 us refresh cycle time t rfcab 130 ns per bank refresh cycle time t rfcpb 60 ns burst refresh window = 4 x 8 x t rfcab t refbw 4.16 us tdqss min derated , () 0.75 tjit per () act min , tjit per () allowed min tck avg () tdqss max derated , () 1.25 tjit per () act max , tjit per () allowed max tck avg () http:/// - 61 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.4 ac timings [table 47] lpddr2 ac timing table parameter symbol min max min t ck lpddr2 unit 800 667 max. frequency *4 ~ 400 333 mhz clock timing average clock period t ck (avg) min 2.5 3 ns max 100 average high pulse width t ch (avg) min 0.45 t ck (avg) max 0.55 average low pulse width t cl (avg) min 0.45 t ck (avg) max 0.55 absolute clock period t ck (abs) min t ck (avg)min -/+ t jit (per)min ps absolute clock high pulse width (with allowed jitter) t ch (abs), allowed min 0.43 t ck (avg) max 0.57 absolute clock low pulse width (with allowed jitter) t cl (abs), allowed min 0.43 t ck (avg) max 0.57 clock period jitter (with allowed jitter) t jit (per), allowed min -100 -110 ps max 100 110 maximum clock jitter between two consecutive clock cycles (with allowed jitter) t jit (cc), allowed max 200 220 ps duty cycle jitter (with allowed jitter) t jit (duty), allowed min min((t ch (abs),min - t ch (avg),min), (t ch (abs),min - t ch (avg),min)) * t ck (avg) ps max max((t ch (abs),max - t ch (avg),max), (t ch (abs),max - t ch (avg),max)) * t ck (avg) ps cumulative error across 2 cycles t err (2per), allowed min -147 -162 ps max 147 162 cumulative error across 3 cycles t err (3per), allowed min -175 -192 ps max 175 192 cumulative error across 4 cycles t err (4per), allowed min -194 -214 ps max 194 214 cumulative error across 5 cycles t err (5per) , allowed min -209 -230 ps max 209 230 cumulative error across 6 cycles t err (6per) , allowed min -222 -244 ps max 222 244 cumulative error across 7 cycles t err (7per) , allowed min -232 -256 ps max 232 256 cumulative error across 8 cycles t err (8per) , allowed min -241 -256 ps max 241 256 cumulative error across 9 cycles t err (9per) , allowed min -249 -274 ps max 249 274 cumulative error across 10 cycles t err (10per) , allowed min -257 -282 ps max 257 282 cumulative error across 11 cycles t err (11per) , allowed min -263 -289 ps max 263 289 cumulative error across 12 cycles t err (12per) , allowed min -269 -296 ps max 269 296 http:/// - 62 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 cumulative error across n = 13, 14 . . . 49, 50 cycles t err (nper) , allowed min terr(nper)min = (1 + 0.68ln(n)) * tjit(per), allowed, min ps max terr(nper)max = (1 + 0.68ln(n)) * tjit(per), allowed, max zq calibration parameters initialization calibration time *14 t zqinit min 1 us full calibration time *14 t zqcl min 6 360 ns short calibration time *14 t zqcs min 6 90 ns calibration reset time *14 t zqreset min 3 50 read parameters *11 dqs output access time from ck/ck# t dqsck min 2500 ps max 5500 dqsck delta short *15 t dqsckds max 450 540 ps dqsck delta medium *16 t dqsckdm max 900 1050 ps dqsck delta long *17 t dqsckdl max 1200 1400 ps dqs - dq skew t dqsq max 240 280 ps data hold skew factor t qhs max 280 340 ps dqs output high pulse width t qsh min t ch (avg) - 0.05 t ck (avg) dqs output low pulse width t qsl min t cl (avg) - 0.05 t ck (avg) data half period t qhp min min(t qsh , t qsl ) t ck (avg) dq / dqs output hold time from dqs t qh min t qhp - t qhs ps read preamble *11,*12 t rpre min 0.9 t ck (avg) read postamble *11,*13 t rpst min t cl - 0.05 t ck (avg) dqs low-z from clock *11 t lz(dqs) min t dqsck(min) - 300 ps dq low-z from clock *11 t lz(dq) min t dqsck(min) - (1.4 * t qhs(max) ) ps dqs high-z from clock *11 t hz(dqs) max t dqsck(max) - 100 ps dq high-z from clock *11 t hz(dq) max t dqsck(max) + (1.4 * t dqsq(max) ) ps write parameters *11 dq and dm input hold time (vref based) t dh min 270 350 ps dq and dm input setup time (vref based) t ds min 270 350 ps dq and dm input pulse width t dipw min 0.35 t ck (avg) write command to 1st dqs latching transition t dqss min 0.75 t ck (avg) max 1.25 dqs input high-level width t dqsh min 0.4 t ck (avg) dqs input low-level width t dqsl min 0.4 t ck (avg) dqs falling edge to ck setup time t dss min 0.2 t ck (avg) dqs falling edge hold time from ck t dsh min 0.2 t ck (avg) write postamble t wpst min 0.4 t ck (avg) write preamble t wpre min 0.35 t ck (avg) cke input parameters cke min. pulse width (high and low pulse width) t cke min 3 3 t ck (avg) cke input setup time t iscke *2 min 0.25 t ck (avg) cke input hold time t ihcke *3 min 0.25 t ck (avg) command address input parameters *11 parameter symbol min max min t ck lpddr2 unit 800 667 http:/// - 63 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 address and control input setup time (vref based) t is *1 min 290 370 ps address and control input hold time (vref based) t ih * 1 min 290 370 ps address and control input pulse width t ipw min 0.40 t ck (avg) boot parameters (10 mhz - 55 mhz) *5,7,8 clock cycle time t ckb max - 100 ns min 18 cke input setup time t isckeb min - 2.5 ns cke input hold time t ihckeb min - 2.5 ps address & control input setup time t isb min - 1150 ps address & control input hold time t ihb min - 1150 ns dqs output data access time from ck/ck# t dqsckb min - 2.0 ns max 10.0 data strobe edge to ouput data edge t dqsqb - 1.2 t dqsqb max - 1.2 ns data hold skew factor t qhsb max - 1.2 ns mode register parameters mode register write command period t mrw min 5 5 t ck (avg) mode register read command period t mrr min 2 2 t ck (avg) lpddr2 sdram core parameters *9 read latency rl min 3 6 5 t ck (avg) write latency wl min 1 3 2 t ck (avg) active to active command period t rc min t ras + t rpab (with all-bank precharge) t ras + t rppb (with per-bank precharge) ns cke min. pulse width during self-refresh (low pulse width during self-refresh) t ckesr min 3 15 ns self refresh exit to next valid command delay t xsr min 2 t rfcab + 10 ns exit power down to next valid command delay t xp min 2 7.5 ns lpddr2-s4 cas to cas delay t ccd min 2 2 t ck (avg) internal read to precharge command delay t rtp min 2 7.5 ns ras to cas delay t rcd min 3 18 ns row precharge time (single bank) t rppb min 3 18 ns row precharge time (all banks) t rpab 4-bank min 3 18 ns row precharge time (all banks) t rpab 8-bank min 3 21 ns row active time t ras min 3 42 ns max - 70 us write recovery time t wr min 3 15 ns internal write to read command delay t wtr min 2 7.5 ns active bank a to active bank b t rrd min 2 10 ns four bank activate window t faw min 8 50 ns minimum deep power down time t dpd min 500 us lpddr2 temperature de-rating t dqsck de-rating t dqsck (derated) max 6000 ps parameter symbol min max min t ck lpddr2 unit 800 667 http:/// figure 15. hsul_12 driver output reference load for timing and slew rate - 64 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 note : 1) input set-up/hold time for signal(ca0 ~ 9, cs ) 2) cke input setup time is measured from cke reaching high/low voltage level to ck/ck crossing. 3) cke input hold time is measured from ck/ck crossing to cke reaching high/low voltage level . 4) frequency values are for reference only. clock cycle time (tck) shall be used to determine device capabilities. 5) to guarantee device operation before the lpddr2 device is c onfigured a number of ac boot ti ming parameters are defined in th e table 47, lpddr2 ac timing table . boot parameter symbols have the letter b appended, e.g. tck during boot is tckb. 6) frequency values are for reference only. clock cycle time (t ck or tckb) shall be used to determeing devuce capabilities. 7) the sdram will set some mode register default values upon receiving a reset (mrw) command as specified in figure 5.2 mode register definition . 8) the output skew parameters are measured with ron default settings into the reference load. 9) the min tck column applies only when tck is greater than 6ns for lpddr2-s4 devices. in this case, both min tck values and an alog timing (ns) shall be satisfied. 10) all ac timings assume an input slew rate of 1v/ns. 11) read, write, and input setup and hold values are referenced to vref. 12) for low-to-high and high-to-low transitions, the timing refer ence will be at the point when the signal crosses vtt. thz and tlz transitions occur in the same access time (with respect to clock) as valid data transitions. these parameters ar e not referenced to a specific voltage level but to the time wh en the device output is no longer driving (for trpst, thz(dqs) and thz(dq) ), or begins driving (for trpre, tlz(dqs), tlz(dq) ). figure 15 shows a method to calculate the point when device is no longer driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq) by measuring the si gnal at two different voltages. the actual voltage measurement points are not critical as long as the calcula- tion is consistent. the parameters tlz(dqs), tlz(dq), thz(dqs), and thz(dq) are defined as single-ended. the timing parameters trpre and trpst are determined from the differential signal dqs-dqs . 13) measured from the start driving of dqs - dqs to the start driving the first rising strobe edge. 14) measured from the start driving the last falling strobe edge to the stop driving dqs - dqs . 15) tdqsckds is the absolute value of the difference between an y two tdqsck measurements (within a byte lane) within a contiguo us sequence of bursts within a 160ns roll- ing window. tdqsckds is not tested and is guaranteed by design. temperature drift in the system is < 10c/s. values do not inclu de clock jitter. 16) tdqsckdm is the absolute value of the difference between an y two tdqsck measurements (within a byte lane) within a 1.6us ro lling window. tdqsckdm is not tested and is guaranteed by design. temperature drift in the syste m is < 10c/s. values do not include clock jitter. 17) tdqsckdl is the absolute value of the difference between any two tdqsck measurements (within a byte lane) within a 32ms rol ling window. tdqsckdl is not tested and is guaranteed by design. temperature drift in the syste m is < 10c/s. values do not include clock jitter. 18) tfaw is only applied in devices with 8 banks. core timings temperature de-rating for sdram t rcd (derated) min t rcd + 1.875 ns t rc (derated) min t rc + 1.875 ns t ras (derated) min t ras + 1.875 ns t rp (derated) min t rp + 1.875 ns t rrd (derated) min t rrd + 1.875 ns parameter symbol min max min t ck lpddr2 unit 800 667 thz(dqs), thz(dq) stop driving point = 2 x t1 - t2 vol + 2x x mv t1 t2 vol + x mv voh - x mv voh - 2x x mv tlz(dqs), tlz(dq) begin driving point = 2 x t1 - t2 vol vtt - y mv voh t2 t1 vtt - 2x y mv vtt + 2x y mv vtt + y mv vtt vtt y 2x y actual waveform x 2x x http:/// - 65 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.5 ca and cs setup, hold and derating for all input signals the total tis (setup time) and tih (hold time ) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 47 ) to the tis and tih derating value (see table 49 and table 50 ) respectively. example: tis (total setup time) = tis(base) + tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tis) nominal slew rate for a fa lling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value (see figure 16 ). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 18 ). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of v ref (dc). hold (tih) nominal slew rate for a falling si gnal is defined as the slew rate between t he last crossing of vih(dc)min and the first crossing of v ref (dc). if the actual signal is always later than the nom inal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value (see figure 17 ). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value (see figure 19 ). for a valid transition the input signal has to remain above/below v ih/il (ac) for some time t vac (see table 50 ). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input sig nal is still required to comp lete the transition and reach v ih/il (ac). for slew rates in between the values listed in table 49 , the derating values may obtai ned by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. [table 48] ca and cs setup and hold base-values for 1v/ns note : 1) ac/dc referenced for 1v/ns ca and cs slew rate and 2v/ns differential ck-ck slew rate. unit [ps] lpddr2 reference 800 667 tis(base) 70 150 vih/l(ac)=vref(dc)+/-220mv tih(base) 160 240 vih/l(dc)=vref(dc)+/-130mv http:/// - 66 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 49] derating values lpddr2 tis/tih - ac/dc based ac220 note : 1) cell contents shaded in red are defined as ?not supported?. [table 50] required time t vac above v ih (ac) {below v il (ac)} for valid transition tis, tih derating in [ps] ac/dc based ac220 threshold -> v ih (ac)=v ref (dc)+220mv, v il (ac)=v ref (dc)-220mv dc100 threshold -> v ih (dc)=v ref (dc)+130mv, v il (dc)=v ref (dc)-130mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih ca slew rate v/ns 2.0 110 65 110 65 110 65 1.57443734373 438959 1.00000 0 0 16163232 0.9 -3 -5 -3 -5 13 11 29 27 45 43 0.8 -8 -13 8 3 241940355655 0.7 2 -6 1810342650466678 0.6 10 -3 26 13 42 33 58 65 0.5 4 -4 20163648 0.4 -7 2 17 34 slew rate [v/ns] t vac @ 220mv [ps] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - < 0.5 150 - http:/// figure 16. illustration of nominal slew rate and t vac for setup time t is for ca and cs with respect to clock. - 67 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssca setup slew rate setup slew rate rising signal falling signal ' tf ' tr v ref (dc) - v il (ac)max ' tf = v ih (ac)min - v ref (dc) ' tr = v ddca v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal nominal slew rate v ref to ac region v ref to ac region tvac tvac slew rate tih tis ck tih tis ck http:/// figure 17. illustration of nominal slew rate for hold time t ih for ca and cs with respect to clock - 68 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssca hold slew rate hold slew rate falling signal rising signal ' tr ' tf v ref (dc) - v il (dc)max ' tr = v ih (dc)min - v ref (dc) ' tf = v ddca v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tih tis ck ck tih tis http:/// figure 18. illustration of tangent line for setup time t is for ca and cs with respect to clock - 69 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssca tih setup slew rate setup slew rate rising signal falling signal ' tf ' tr tangent line[ v ref (dc) - v il (ac)max] ' tf = tangent line[v ih (ac)min - v ref (dc) ] ' tr = v ddca v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tis tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac ck ck tih tis http:/// figure 19. illustration of tangent line for for hold time t ih for ca and cs with respect to clock - 70 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssca hold slew rate ' tf ' tr tangent line [ v ih (dc)min - v ref (dc) ] ' tf = v ddca v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc) max ] ' tr = rising signal tih tis ck ck tih tis http:/// - 71 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 15.6 data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 51 ) to the tds and tdh (see table 52 and table 54 ) derating value respectively. example: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tds) nominal slew rate for a falling signal is def ined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max (see figure 20 ). if the actual signal is always earlier t han the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 22 ). hold (tdh) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref (dc). hold (tdh) nominal slew rate for a falling signal is de fined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref (dc) (see figure 21 ). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref (dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value (see figure 23 ). for a valid transition the input signal has to remain above/below v ih/il (ac) for some time t vac (see table 53 ). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input sig nal is still required to comp lete the transition and reach v ih/il (ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization [table 51] data setup and hold base-values note : 1) ac/dc referenced for 1v/ns ca slew rate and 2v/ns differential dqs-dqs slew rate. [ps] lpddr2 reference 800 667 tds(base) 50 130 vih/l(ac)=vref(dc)+/-220mv tdh(base) 140 220 vih/l(dc)=vref(dc)+/-130mv http:/// - 72 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 [table 52] derating values lpddr2 tds/tdh - ac/dc based ac220 note : 1) cell contents shaded in red are defined as ?not supported?. [table 53] required time t vac above v ih (ac) {below v il (ac)} for valid transition tds, dh derating in [ps] ac/dc based 1) ac220 threshold -> v ih (ac)=v ref (dc)+220mv, v il (ac)=v ref (dc)-220mv dc130 threshold -> v ih (dc)=v ref (dc)+130mv, v il (dc)=v ref (dc)-130mv dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.57443734373 438959 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -3 -5 -3 -5 131129274543 - - - - 0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 261342335865 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 slew rate [v/ns] t vac @ 220mv [ps] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - < 0.5 150 - http:/// figure 20. illustration of nominal slew rate and t vac for setup time t ds for dq with respect to strobe - 73 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssq setup slew rate setup slew rate rising signal falling signal ' tf ' tr v ref (dc) - v il (ac) max ' tf = v ih (ac) min - v ref (dc) ' tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal nominal slew rate v ref to ac region v ref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds http:/// figure 21. illustration of nominal slew rate for hold time t dh for dq with respect to strobe - 74 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssq hold slew rate hold slew rate falling signal rising signal ' tr ' tf v ref (dc) - v il (dc) max ' tr = v ih (dc) min - v ref (dc) ' tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds http:/// figure 22. illustration of tangent line for setup time t ds for dq with respect to strobe - 75 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssq tdh setup slew rate setup slew rate rising signal falling signal ' tf ' tr tangent line[ v ref (dc) - v il (ac)max ' tf = tangent line[v ih (ac) min - v ref (dc) ' tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds http:/// figure 23. illustration of tangent line for for hold time t dh for dq with respect to strobe - 76 - K4P4G304EC-fgc1 datasheet lpddr2-s4 sdram preliminary rev. 0.5 v ssq hold slew rate ' tf ' tr tangent line [ v ih (dc) min - v ref (dc) ] ' tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc) max ] ' tr = rising signal tdh tds dqs dqs tdh tds http:/// |
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